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LTC4101 Datasheet(PDF) 5 Page - Linear Technology

Part # LTC4101
Description  Smart Battery Charger Controller
Download  28 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC4101 Datasheet(HTML) 5 Page - Linear Technology

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LTC4101
5
4101f
The
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 4V unless otherwise noted. (Note 4)
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: See Test Circuit.
Note 3: Does not include tolerance of current sense resistor.
Note 4: The LTC4101E is guaranteed to meet performance specifications
from 0
°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: Current accuracy dependent upon circuit compensation and sense
resistor.
Note 6: CTH is defined as the sum of capacitance on THA, THB and
SafetySignal.
Note 7: The corresponding overrange bit will be set when a HEX value
greater than or equal to this value is used.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logic Levels
VIL
SCL/SDA Input Low Voltage
VDD = 3V and VDD = 5.5V
0.8
V
VIH
SCL/SDA Input High Voltage
VDD = 3V and VDD = 5.5V
2.1
V
VOL
SDA Output Low Voltage
IPULL-UP = 350µA
0.4
V
IIL
SCL/SDA Input Current
VSDA, VSCL = VIL
–1
1
µA
IIH
SCL/SDA Input Current
VSDA, VSCL = VIH
–1
1
µA
VOL
SMBALERT Output Low Voltage
IPULL-UP = 500µA
0.4
V
SMBALERT Output Pull-Up Current
VSMBALERT = VOL
–17.5
–10
–3.5
µA
ILEAK
SDA/SCL/SMBALERT Power Down Leakage
VSDA, VSCL, VSMBALERT = 5.5V, VDD = OV
–2
2
µA
VOL
CHGEN Output Low Voltage
IOL = 100µA
0.5
V
CHGEN Output Pull-Up Current
VCHGEN = VOL
–17.5
–10
–3.5
µA
VIL
CHGEN Input Low Voltage
0.9
V
VIH
CHGEN Input High Voltage
VDD = 3V
2.5
V
VDD = 5.5V
3.9
V
Power-On Reset Duration
VDD Ramp from 0V to >3V in <5µs
100
µs
SMBus Timing (Refer to System Management Bus Specification, Revision 1.1, Section 2.1 for Timing Diagrams)
tHIGH
SCL Serial Clock High Period
IPULL-UP = 350µA, CLOAD = 250pF, RPU = 9.31k,
4
µs
VDD = 3V and VDD = 5.5V
tLOW
SCL Serial Clock Low Period
IPULL-UP = 350µA, CLOAD = 250pF, RPU = 9.31k,
4.7
15000
µs
VDD = 3V and VDD = 5.5V
tR
SDA/SCL Rise Time
CLOAD = 250pF, RPU = 9.31k, VDD = 3V
1000
ns
and VDD = 5.5V
tF
SDA/SCL Fall Time
CLOAD = 250pF, RPU = 9.31k, VDD = 3V
300
ns
and VDD = 5.5V
tSU:STA
Start Condition Setup Time
VDD = 3V and VDD = 5.5V
4.7
µs
tHD:STA
Start Condition Hold Time
VDD = 3V and VDD = 5.5V
4
µs
tHD:DAT
SDA to SCL Falling-Edge Hold Time,
VDD = 3V and VDD = 5.5V
300
ns
Slave Clocking in Data
tTIMEOUT
Time Between Receiving Valid
VDD = 3V and VDD = 5.5V
140
175
210
sec
ChargingCurrent() and
ChargingVoltage() Commands


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