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LTC4085EDE-1-TRPBF Datasheet(PDF) 9 Page - Linear Technology

Part # LTC4085EDE-1-TRPBF
Description  USB Power Manager with Ideal Diode Controller and 4.1V Li-Ion Charger
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC4085EDE-1-TRPBF Datasheet(HTML) 9 Page - Linear Technology

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LTC4085-1
9
40851f
WALL (Pin 7): Wall Adapter Present Input. Pulling this
pin above 4.25V will disconnect the power path from IN
to OUT. The ACPR pin will also be pulled low to indicate
that a wall adapter has been detected.
NTC (Pin 8): Input to the NTC Thermistor Monitoring
Circuits. The NTC pin connects to a negative temperature
coeffcient thermistor which is typically co-packaged with
the battery pack to determine if the battery is too hot or
too cold to charge. If the battery’s temperature is out of
range, charging is paused until the battery temperature re-
enters the valid range. A low drift bias resistor is required
from VNTC to NTC and a thermistor is required from NTC
to ground. If the NTC function is not desired, the NTC pin
should be grounded.
VNTC (Pin 9): Output Bias Voltage for NTC. A resistor from
this pin to the NTC pin will bias the NTC thermistor.
ACPR (Pin 10): Wall Adapter Present Output. Active low
open drain output pin. A low on this pin indicates that the
wall adapter input comparator has had its input pulled
above the input threshold. This feature is disabled if no
power is present on IN or OUT or BAT (i.e., below UVLO
thresholds).
CHRG (Pin 11): Open-Drain Charge Status Output. When
the battery is being charged, the CHRG pin is pulled low by
an internal N-channel MOSFET. When the timer runs out or
the charge current drops below 10% of the programmed
charge current (while in voltage mode) or the input supply
or output supply is removed, the CHRG pin is forced to a
high impedance state.
PI FU CTIO S
PROG (Pin 12): Charge Current Program. Connecting a
resistor, RPROG, to ground programs the battery charge
current. The battery charge current is programmed as
follows:
IA
V
R
CHG
PROG
()
,
=
50 000
GATE (Pin 13): External Ideal Diode Gate Pin. This pin
can be used to drive the gate of an optional external
PFET connected between BAT and OUT. By doing so, the
impedance of the ideal diode between BAT and OUT can be
reduced. When not in use, this pin should be left floating.
It is important to maintain a high impedance on this pin
and minimize all leakage paths.
BAT (Pin 14): Connect to a single cell Li-Ion battery. This
pin is used as an output when charging the battery and
as an input when supplying power to OUT. When the OUT
pin potential drops below the BAT pin potential, an ideal
diode function connects BAT to OUT and prevents VOUT
from dropping significantly below VBAT.Aprecisioninternal
resistor divider sets the final float (charging) potential on
this pin. The internal resistor divider is disconnected when
IN and OUT are in undervoltage lockout.
Exposed Pad (Pin 15): Ground. The exposed package pad
is ground and must be soldered to the PC board for proper
functionality and for maximum heat transfer.


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