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LTC3836EGN-TRPBF Datasheet(PDF) 6 Page - Linear Technology |
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LTC3836EGN-TRPBF Datasheet(HTML) 6 Page - Linear Technology |
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6 / 28 page  LTC3836 6 3836fa PIN FUNCTIONS SW1/SW2 (Pins 1, 14)/(Pins 26, 11): Switch Node Connection to Inductor and External MOSFETs. Also the negative input to differential peak current comparator and an input to the reverse current comparator. Normally connected to the source of the main MOSFET, the drain of the synchronous MOSFET, and the inductor. NC (Pins 2, 18)/(Pins 16, 28): No Connection. IPRG1/IPRG2 (Pins 3, 6)/(Pins 27, 3): Three-State Pins to Select Maximum Peak Sense Voltage Threshold. These pins select the maximum allowed voltage drop between the SENSE+ and SW pins (i.e., the maximum allowed drop across the external main MOSFET) for each channel. Tie to VIN, GND or float to select 202mV, 82mV, or 122mV respectively. VFB1/VFB2 (Pins 4, 11)/(Pins 1, 8): Feedback Pins. Receives the remotely sensed feedback voltage for its con- troller from an external resistor divider across the output. ITH1/ITH2 (Pins 5, 12)/(Pins 2, 9): Current Threshold and Error Amplifier Compensation Point. Nominal operat- ing range on these pins is from 0.7V to 2V. The voltage on these pins determines the threshold of the main current comparator. PLLLPF (Pin 7)/(Pin 4): Frequency Set/PLL Lowpass Filter. When synchronizing to an external clock, this pin serves as the lowpass filter point for the phase-locked loop. Normally a series RC is connected between this pin and ground. When not synchronizing to an external clock, this pin serves as the frequency select input. Tying this pin to GND selects 300kHz operation; tying this pin to VIN selects 750kHz operation. Floating this pin selects 550kHz operation. SGND (Pin 8)/(Pin 5): Small-Signal Ground. This pin serves as the ground connection for most internal circuits. VIN (Pin 9)/(Pin 6): Small-Signal Power Supply. This pin powers the entire chip except for the gate drivers. Externally filtering this pin with a lowpass RC network (e.g., R = 10Ω, C = 1μF) is suggested to minimize noise pickup, especially in high load current applications. TRACK/SS2 (Pin 10)/(Pin 7): Channel 2 Tracking and Soft- Start Input. The LTC3836 regulates the VFB2 voltage to the (GN Package)/(UFD Package) smaller of 0.6V or the voltage on the TRACK/SS2 pin. An internal 1.5μA pull-up current source is connected to this pin. A capacitor to ground at this pin sets the ramp time to final regulated output voltage. Alternatively, a resistor divider on another voltage supply connected to this pin allows the LTC3836 output to track the other supply dur- ing start-up. PGOOD (Pin 13)/(Pin 10): Power-Good Output Voltage Monitor Open-Drain Logic Output. This pin is pulled to ground when the voltage on either feedback pin (VFB1, VFB2) is not within ±13.3% of its nominal set point. PGND (Pins 17, 22, 26)/(Pins 14, 19, 23): Power Ground. These pins serve as the ground connection for the gate drivers and the negative input to the reverse current comparators. The Exposed Pad must be soldered to PCB ground. RUN/SS (Pin 20)/(Pin 17): Run Control Input and Op- tional External Soft-Start Input. Forcing this pin below 0.65V shuts down the chip (both channels). Driving this pin to VIN or releasing this pin enables the chip, using the chip’s internal soft-start. An external soft-start can be programmed by connecting a capacitor between this pin and ground. TG1/TG2 (Pins 23, 21)/(Pins 20, 18): Top Gate Drive Output. These pins drive the gates of the external topside MOSFETs. These pins have an output swing from PGND to BOOST. SYNC/FCB (Pin 24)/(Pin 21): This pin performs two functions: 1) external clock synchronization input for phase-locked loop, and 2) pulse-skipping operation or forced continuous mode select. To synchronize with an external clock using the PLL, apply a CMOS compatible clock with a frequency between 250kHz and 850kHz. To select pulse-skipping operation at light loads, tie this pin to VIN. Grounding this pin selects forced continuous operation, which allows the inductor current to reverse. When synchronized to an external clock, pulse-skipping operation is enabled at light loads. BG1/BG2 (Pins 25, 19)/(Pins 22, 15): Bottom Gate Drive Output. These pins drive the gates of the external synchronous MOSFETs. These pins have an output swing from PGND to BOOST. |
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