PE43703MLI-Z datasheet(11/15 Pages) PEREGRINE

Part #	PE43703MLI-Z

Description	50 廓 RF Digital Attenuator 7-bit, Product Description 31.75 dB, DC-6.0 GHz

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Manufacturer	PEREGRINE [Peregrine Semiconductor Corp.]

Direct Link	http://www.peregrine-semi.com

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11 / 15 page

Product Specification

PE43703

Page 11 of 15

Document No. 70-0245-04

│ www.psemi.com

Table 14. Parallel and Direct Interface AC

Table 13. Serial Interface AC Characteristics

Note:

fClk is verified during the functional pattern test. Serial

programming sections of the functional pattern are clocked

at 10 MHz to verify fclk specification.

VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified

Figure 29. Serial-Addressable Timing Diagram

Figure 30. Latched-Parallel/Direct-Parallel Timing Diagram

Symbol

Parameter

Min

Max

Unit

FCLK

Serial clock frequency

-

10

MHz

TCLKH

Serial clock HIGH time

30

-

ns

TCLKL

Serial clock LOW time

30

-

ns

TLESU

Last serial clock rising edge

setup time to Latch Enable

rising edge

10

-

ns

TLEPW

Latch Enable min. pulse width

30

-

ns

TSISU

Serial data setup time

10

-

ns

TSIH

Serial data hold time

10

-

ns

TDISU

Parallel data setup time

100

-

ns

TDIH

Parallel data hold time

100

-

ns

TASU

Address setup time

100

-

ns

TAH

Address hold time

100

-

ns

TPSSU

Parallel/Serial setup time

100

-

ns

TPSH

Parallel/Serial hold time

100

-

ns

TPD

Digital register delay (internal)

-

10

ns

Symbol

Parameter

Min

Max

Unit

TLEPW

Latch Enable minimum

pulse width

30

-

ns

TDISU

Parallel data setup time

100

-

ns

TDIH

Parallel data hold time

100

-

ns

TPSSU

Parallel/Serial setup time

100

-

ns

TPSIH

Parallel/Serial hold time

100

-

ns

TPD

Digital register delay

(internal)

-

10

ns

TDIPD

Digital register delay

(internal, direct mode only)

-

5

ns

Characteristics

VALID

T

DISU

T

DIH

DI[6:0]

LE

P/S

T

PSSU

T

PSH

T

LEPW

VALID

DO[6:0]

T

DIPD

T

PD

Bits can either be set to logic high or logic low

A[2]

A[1]

A[0]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

T

SISU

T

CLKL

T

LEPW

T

SIH

T

CLKH

SI

CLK

LE

P/S

T

LESU

T

PSSU

T

PSH

VALID

T

ASU

ADD[2:0]

T

AH

DO[6:0]

VALID

DI[6:0]

T

PD

T

DISU

T

DIH

D[0]

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