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LV5544DEV-125.0M-1K Datasheet(PDF) 6 Page - Pletronics, Inc. |
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LV5544DEV-125.0M-1K Datasheet(HTML) 6 Page - Pletronics, Inc. |
6 / 8 page LV55D Series 3.3 V LVDS Clock Oscillators September 2007 www.pletronics.com 425-776-1880 6 3 4 1 2 6 5 Mechanical: Inches mm A 0.197 + _0.006 5.00 + _0.15 B 0.125 + _0.006 3.20 + _0.15 C 0.053 max 1.35 max D 1 0.050 1.27 E 1 0.050 1.27 F 1 0.004 0.10 G 1 0.039 1.00 H 1 0.025 0.63 Contacts : Gold 11.8 µinches 0.3 µm minimum over Nickel 50 to 350 µinches 1.27 to 8.89 µm 1 Typical dimensions Not to Scale I 1 0.020 0.50 J 1 0.004R 0.10R K 1 0.008R 0.20R Pad Function Note 1 Output Enable/Disable When this pad is not connected the oscillator shall operate. When this pad is <0.30 volts, the output will be inhibited (high impedance state.) Recommend connecting this pad to V CC if the oscillator is to be always on. 2 No connect There is no internal connection to this pad 3 Ground (GND) 4 Output The outputs must be terminated, 100 ohms between the outputs is the ideal termination. 5 Output* 6 Supply Voltage (V CC) Recommend connecting appropriate power supply bypass capacitors as close as possible. Layout and application information Recommend connecting Pad 1 and Pad 2 together to permit the design to accept Enable/Disable on both input pads For Optimum Jitter Performance, Pletronics recommends: • a ground plane under the device • no large transient signals (both current and voltage) should be routed under the device • do not layout near a large magnetic field such as a high frequency switching power supply • do not place near piezoelectric buzzers or mechanical fans. |
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