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LTC3524EUF-TRPBF Datasheet(PDF) 6 Page - Linear Technology |
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LTC3524EUF-TRPBF Datasheet(HTML) 6 Page - Linear Technology |
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6 / 16 page  LTC3524 6 3524f PIN FUNCTIONS VIN (Pin 2): Common Input Supply for LCD Bias and White LED Boost Converters. This pin must be locally bypassed with a minimum of 2.2μF. GND/Exposed Pad (Pin 25): Signal and Power Ground for the LTC3524. Provide a short, direct PCB path between GND and the (–) side of the boost (VOUT, VLED) filter capaci- tors, and the (–) side of the charge pump outputs (V2x, VH, VN) filter capacitors. PCB ground must be soldered to the Exposed Pad for proper operation. ELCD (Pin 1): Enable Input for the LTC3524’s LCD Cir- cuits. LCD bias supplies are actively discharged to GND when ELCD is low through internal pull down devices. An optional RC network on ELCD provides a slower ramp-up of the LCD boost converter inductor current during start- up (soft-start). Shutdown mode is activated by driving ELCD, ELED1, and ELED2 low. Shutdown disables all IC functions and reduces quiescent current from the battery to less than 2μA. FBVO (Pin 3): Feedback Pin for the VOUT Switcher. Refer- ence voltage is 1.225V. Connect resistive divider tap here with minimum trace area. V R R See Block Diagram OUT =+ ⎛ ⎝⎜ ⎞ ⎠⎟ 1 225 1 1 2 .( ) VOUT (Pin 4): Main Output of the LCD Boost Regulator and Input to the Voltage Doubler (2X) Stage. Bypass VOUT with a low ESR, ESL ceramic capacitor (X5R type) between 4.7 and 22μF. SW1 (Pin 5): Synchronous Boost Switch. Connect a 4.7μH-15μH inductor between SW1 and VIN. Keep PCB trace lengths as short and wide as possible to reduce EMI and voltage overshoot. If the inductor current falls to zero, the PMOS synchronous rectifier is turned off to prevent reverse charging of the inductor and an internal switch connects SW1 to VIN to reduce EMI. C2– (Pin 6): Charge pump doubler flying capacitor negative node. The charge pump doubler flying capacitor is con- nected between C2+ and C2–. The voltage on C2– will alter- nate between GND and VOUT at an approximate 50% duty cycle while the charge pump is operating. Use a 0.1μF X5R type ceramic capacitor for best results. LCD BIAS PIN FUNCTIONS C2+ (Pin 7): Charge pump doubler flying capacitor posi- tive node. The charge pump doubler flying capacitor is connected between C2+ and C2–. The voltage on C2+ will alternate between VOUT and V2x at an approximate 50% duty cycle while the charge pump is operating. Use a 0.1μF X5R type ceramic capacitor for best results. V2x (Pin 8): Charge Pump Doubler Output and Input to the Charge Pump Quadrupler. This output generates 2X VOUT. V2x should be bypassed to GND with a 0.47μF X5R type ceramic capacitor. C2+ and C2– should be left open and V2x connected to VOUT if the doubler is not needed to generate VH or VN. VNIN (Pin 9): Positive Voltage Input for the Charge Pump Inverter. The charge pump inverter can generate a regu- lated negative voltage up to the voltage applied to VNIN. Connect VNIN to VOUT, V2x, or VH. If VNIN is connected to VH, external diodes and a capacitor are required for sequencing (see the Applications Information section). CN+ (Pin 10): Charge Pump Inverter Flying Capacitor Positive Node. The charge pump inverter flying capacitor is connected between CN+ and external Schottky diodes (see Typical Application figures). The voltage on CN+ will alternate between GND and VNIN at an approximate 50% duty cycle while the inverting charge pump is operating. Use a 0.1μF X5R type ceramic capacitor for best results. NC (PIN 11): No Connect. This pin should be connected to GND. VN (Pin 12): Negative Charge Pump Converter Output. VN can be regulated down to approximately –VNIN volts depending on where VNIN is connected. VN should be bypassed to GND with at 0.47μF or larger X5R type ce- ramic capacitor. |
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