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LTC2923IDE Datasheet(PDF) 7 Page - Linear Technology |
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LTC2923IDE Datasheet(HTML) 7 Page - Linear Technology |
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7 / 20 page  LTC2923 7 2923fa APPLICATIO S I FOR ATIO Power Supply Tracking and Sequencing The LTC2923 handles a variety of power-up profiles to satisfy the requirements of digital logic circuits including FPGAs, PLDs, DSPs and microprocessors. These require- ments fall into one of the four general categories illus- trated in Figures 1 to 4. Some applications require that the potential difference between two power supplies must never exceed a speci- fied voltage. This requirement applies during power-up and power-down as well as during steady-state operation, often to prevent destructive latch-up in a dual supply ASIC. Typically, this is achieved by ramping the supplies up and down together (Figure 1). In other applications it is desir- able to have the supplies ramp up and down with fixed voltage offsets between them (Figure 2) or to have them ramp up and down ratiometrically (Figure 3). Certain applications require one supply to come up after another. For example, a system clock may need to start before a block of logic. In this case, the supplies are sequenced as in Figure 4 where the 2.5V supply ramps up after the 1.8V supply is completely powered. Operation The LTC2923 provides a simple solution to all of the power supply tracking and sequencing profiles shown in Figures 1 to 4. A single LTC2923 controls up to three supplies with two “slave” supplies that track a “master” signal. With just two resistors, a slave supply is configured to ramp up as a function of the master signal. This master signal can be a third supply that is ramped up through an external FET, whose ramp rate is set with a single capacitor, or it can be a signal generated by tying the GATE and RAMP pins to an external capacitor. 1V/DIV 1ms/DIV 2923 F01 Figure 1. Coincident Tracking 1V/DIV 1ms/DIV 2923 F02 Figure 2. Offset Tracking 1V/DIV 1ms/DIV 2923 F03 Figure 3. Ratiometric Tracking 1V/DIV 1ms/DIV 2923 F04 Figure 4. Supply Sequencing MASTER SLAVE1 SLAVE2 MASTER SLAVE1 SLAVE2 MASTER SLAVE1 SLAVE2 SLAVE1 SLAVE2 |
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