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LTC2485CDD Datasheet(PDF) 11 Page - Linear Technology |
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LTC2485CDD Datasheet(HTML) 11 Page - Linear Technology |
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11 / 40 page  11 LTC2485 2485fa FU CTIO AL BLOCK DIAGRA PI FU CTIO S REF+ (Pin 1), REF– (Pin 3): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, is more positive than the reference negative input, REF –, by at least 0.1V. VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 8) with a 1 µF tantalum capacitor in parallel with 0.1µF ceramic capacitor as close to the part as possible. IN+ (Pin 4), IN– (Pin 5): Differential Analog Input. The voltage on these pins can have any value between GND – 0.3V and VCC + 0.3V. Within these limits the converter bipolar input range (VIN = IN+ – IN–) extends from –0.5 • VREF to 0.5 • VREF. Outside this input range the converter produces unique overrange and underrange output codes. SCL (Pin 6): Serial Clock Pin of the I2C Interface. The LTC2485 can only act as a slave and the SCL pin only accepts external serial clock. Data is shifted into the SDA pin on the rising edges of the SCL clock and output through the SDA pin on the falling edges of the SCL clock. SDA (Pin 7): Bidirectional Serial Data Line of the I2C Interface. In the transmitter mode (Read), the conversion result is output through the SDA pin, while in the receiver mode (Write), the device configuration bits are input through the SDA pin. At data input mode, the pin is high impedance; while at data output mode, it is an open-drain N-channel driver and therefore an external pull-up resistor or current source to VCC is needed. GND (Pin 8): Ground. Connect this pin to a ground plane through a low impedance connection. CA1 (Pin 9): Chip Address Control Pin. The CA1 pin is configured as a three state (LOW, HIGH, or Floating) address control bit for the device I2C address. CA0/F0 (Pin 10): Chip Address Control Pin/External Clock Input Pin. When no transition is detected on the CA0/F0 pin, it is a two state (HIGH or Floating) address control bit for the device I2C address. When the pin is driven by an external clock signal with a frequency fEOSC of at least 10kHz, the converter uses this signal as its system clock and the fundamental digital filter rejection null is located at a frequency fEOSC/5120 and sets the Chip Address CA0 internally to a HIGH. 6 7 4 5 9 10 3RD ORDER ∆ΣADC REF+ IN+ IN+ 1 REF+ IN– IN– REF– I2C SERIAL INTERFACE TEMP SENSOR MUX SCL 2 VCC 3 REF– 8 GND CA0/F0 2485 FB SDA CA1 AUTOCALIBRATION AND CONTROL INTERNAL OSCILLATOR |
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Similar Description - LTC2485CDD |
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