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LTC2362ITS8-TRMPBF Datasheet(PDF) 5 Page - Linear Technology |
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LTC2362ITS8-TRMPBF Datasheet(HTML) 5 Page - Linear Technology |
5 / 20 page LTC2360/LTC2361/LTC2362 5 236012f TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: When pins AIN and VREF are taken below GND or above VDD, they will be clamped by internal diodes. These products can handle input currents greater than 100mA below GND or above VDD without latch-up. Note 4: VDD = OVDD = VREF = 2.35V to 3.6V, fSMPL = fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise specified. Note 5: Integral linearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. SYMBOL PARAMETER CONDITIONS LTC2360 LTC2361 LTC2362 UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX fSMPL(MAX) Maximum Sampling Frequency (Notes 8, 9) l 100 250 500 kHz fSCK Shift Clock Frequency (Notes 8, 9) l 10 25 50 MHz tSCK Shift Clock Period l 100 40 20 ns tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV l 10 4 2 μs tACQ Acquisition Time l 2 1 0.5 μs tCONV Conversion Time l 8 3 1.5 μs t1 Minimum Positive CONV Pulse Width (Note 8) l 8 3 1.5 μs t2 SCK↑ Setup Time After CONV↓ (Note 8) l 16 16 16 ns t3 SDO Enabled Time After CONV↓ (Notes 8, 9) l 16 16 16 ns t4 SDO Data Valid Access Time After SCK↓ (Notes 8, 9, 10) l 888 ns t5 SCK Low Time (Note 11) l 40% 40% 40% tSCK t6 SCK High Time (Note 11) l 40% 40% 40% tSCK t7 SDO Data Valid Hold Time After SCK↓ (Notes 8, 9, 10) l 444 ns t8 SDO Into Hi-Z State Time After CONV↑ (Notes 8, 9) 6 6 6 ns Note 6: Linearity, offset and gain specifications apply for a single-ended AIN input with respect to GND. Note 7: Typical RMS noise at code transitions. Note 8: Guaranteed by characterization. All input signals are specified with tr = tf = 2ns (10% to 90% of VDD) and timed from a voltage level of 1.6V. Note 9: All timing specifications given are with a 10pF capacitance load. With a capacitance load greater than this value, a digital buffer or latch must be used. Note 10: The time required for the output to cross the VIH or VIL voltage. Note 11: Guaranteed by design, not subject to test. Note 12: High temperatures degrade operating lifetimes. Operating lifetime is derated at temperatures greater than 105°C. |
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