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LTC2289IUP Datasheet(PDF) 1 Page - Linear Technology |
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LTC2289IUP Datasheet(HTML) 1 Page - Linear Technology |
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1 / 24 page  LTC2289 1 2289fa , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. FEATURES DESCRIPTIO APPLICATIO S TYPICAL APPLICATIO ■ Integrated Dual 10-Bit ADCs ■ Sample Rate: 80Msps ■ Single 3V Supply (2.7V to 3.4V) ■ Low Power: 422mW ■ 61.6dB SNR at 70MHz Input ■ 85dB SFDR at 70MHz Input ■ 110dB Channel Isolation at 100MHz ■ Multiplexed or Separate Data Bus ■ Flexible Input: 1VP-P to 2VP-P Range ■ 575MHz Full Power Bandwidth S/H ■ Clock Duty Cycle Stabilizer ■ Shutdown and Nap Modes ■ Pin Compatible Family 105Msps: LTC2282 (12-Bit), LTC2280 (10-Bit) 80Msps: LTC2294 (12-Bit), LTC2289 (10-Bit) 65Msps: LTC2293 (12-Bit), LTC2288 (10-Bit) 40Msps: LTC2292 (12-Bit), LTC2287 (10-Bit) 25Msps: LTC2291 (12-Bit), LTC2286 (10-Bit) ■ 64-Pin (9mm × 9mm) QFN Package Dual 10-Bit, 80Msps Low Noise 3V ADC The LTC ®2289 is a 10-bit 80Msps, low noise 3V dual A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2289 is perfect for demanding imaging and communications applications with AC performance that includes 61.6dB SNR and 85dB SFDR for signals well beyond the Nyquist frequency. DC specs include ±0.1LSB INL (typ), ±0.1LSB DNL (typ) and ±0.6LSB INL, ±0.5LSB DNL over temperature. The transition noise is a low 0.08LSBRMS. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic. An optional multiplexer allows both channels to share a digital output bus. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high perfor- mance at full speed for a wide range of clock duty cycles. SNR vs Input Frequency, –1dB, 2V Range, 80Msps INPUT FREQUENCY (MHz) 0 55 56 58 59 60 65 62 50 100 2289 TA02 57 63 64 61 150 200 ■ Wireless and Wired Broadband Communication ■ Imaging Systems ■ Spectral Analysis ■ Portable Instrumentation – + INPUT S/H ANALOG INPUT A ANALOG INPUT B CLK A CLK B 10-BIT PIPELINED ADC CORE CLOCK/DUTY CYCLE CONTROL OUTPUT DRIVERS • • • OVDD OGND MUX D9A D0A • • • OVDD OGND 2289 TA01 D9B D0B – + OUTPUT DRIVERS INPUT S/H 10-BIT PIPELINED ADC CORE CLOCK/DUTY CYCLE CONTROL |
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