LTC2285IUP datasheet(5/24 Pages) LINER

Part #	LTC2285IUP

Description	Dual 14-Bit, 135Msps Low Power 3.3V ADC

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Manufacturer	LINER [Linear Technology]

Direct Link	http://www.linear.com

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LTC2285IUP#3CGPBF

5

2285iup#3cgpbf

The

l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Note 8)

POWER REQUIREMENTS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VDD

Analog Supply Voltage

(Note 9)

●

2.85

3.3

3.4

V

OVDD

Output Supply Voltage

(Note 9)

●

0.5

3.3

3.6

V

IVDD

Supply Current

Both ADCs at fS(MAX)

●

289

325

mA

PDISS

Power Dissipation

Both ADCs at fS(MAX)

●

954

1072

mW

PSHDN

Shutdown Power (Each Channel)

SHDN = H, OE = H, No CLK

2

mW

PNAP

Nap Mode Power (Each Channel)

SHDN = H, OE = L, No CLK

15

mW

The

l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Note 4)

TIMING CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fs

Sampling Frequency

(Note 9)

●

1

135

MHz

tL

CLK Low Time

Duty Cycle Stabilizer Off (Note 7)

Duty Cycle Stabilizer On (Note 7)

●

3.5

3

3.7

500

ns

tH

CLK High Time

Duty Cycle Stabilizer Off (Note 7)

Duty Cycle Stabilizer On (Note 7)

●

3.5

3

3.7

500

ns

tAP

Sample-and-Hold Aperture Delay

0

ns

tD

CLK to DATA Delay

CL = 5pF (Note 7)

●

1.4

2.7

5.4

ns

tC

CLK to CLKOUT Delay

CL = 5pF (Note 7)

●

1.4

2.7

5.4

ns

DATA to CLKOUT Skew

(tD – tC) (Note 7)

●

–0.6

0

0.6

ns

tMD

MUX to DATA Delay

CL = 5pF (Note 7)

●

1.4

2.7

5.4

ns

Data Access Time After OE

↓

CL = 5pF (Note 7)

●

4.3

10

ns

BUS Relinquish Time

(Note 7)

●

3.3

8.5

ns

Pipeline Latency

5

Cycles

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground with GND and OGND

wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above VDD, they

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above VDD without latchup.

Note 4: VDD = 3.3V, fSAMPLE = 135MHz, input range = 2VP-P with

differential drive, unless otherwise noted.

Note 5: Integral nonlinearity is deﬁned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 6: Offset error is the offset voltage measured from –0.5 LSB when

the output code ﬂickers between 00 0000 0000 0000 and

11 1111 1111 1111.

Note 7: Guaranteed by design, not subject to test.

Note 8: VDD = 3.3V, fSAMPLE = 135MHz, input range = 1VP-P with

differential drive. The supply current and power dissipation are the

sum total for both channels with both channels active.

Note 9: Recommended operating conditions.

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