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LTC2241IUP-12 Datasheet(PDF) 3 Page - Linear Technology |
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LTC2241IUP-12 Datasheet(HTML) 3 Page - Linear Technology |
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3 / 28 page  3 LTC2241-12 224112fa SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SNR Signal-to-Noise Ratio (Note 10) 10MHz Input 65.5 dB 70MHz Input ● 64 65.4 dB 140MHz Input 65.4 dB 240MHz Input 65.2 dB SFDR Spurious Free Dynamic Range 10MHz Input 78 dB 2nd or 3rd Harmonic 70MHz Input ● 65 74 dB (Note 11) 140MHz Input 73 dB 240MHz Input 72 dB Spurious Free Dynamic Range 10MHz Input 87 dB 4th Harmonic or Higher 70MHz Input ● 74 87 dB (Note 11) 140MHz Input 87 dB 240MHz Input 87 dB S/(N+D) Signal-to-Noise Plus 10MHz Input 65.4 dB Distortion Ratio 70MHz Input ● 62.1 65.2 dB (Note 12) 140MHz Input 65.1 dB 240MHz Input 64.9 dB IMD Intermodulation Distortion fIN1 = 135MHz, fIN2 = 140MHz 81 dBc DY A IC ACCURACY The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) ● 12 Bits Integral Linearity Error Differential Analog Input (Note 5) ● –2.3 ±0.7 2.3 LSB Differential Linearity Error Differential Analog Input ● –1 ±0.4 1 LSB Offset Error (Note 6) ● –15 ±515 mV Gain Error External Reference ● –3.4 ±0.7 3.4 %FS Offset Drift ±10 µV/C Full-Scale Drift Internal Reference ±60 ppm/C External Reference ±45 ppm/C Transition Noise SENSE = 1V 0.74 LSBRMS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Analog Input Range (AIN+ – AIN–) 2.375V < VDD < 2.625V (Note 7) ● ±0.5 to ±1V VIN, CM Analog Input Common Mode (AIN+ + AIN–)/2 Differential Input (Note 7) ● 1.2 1.25 1.3 V IIN Analog Input Leakage Current 0 < AIN+, AIN– < VDD ● –1 1 µA ISENSE SENSE Input Leakage 0V < SENSE < 1V ● –1 1 µA IMODE MODE Pin Pull-Down Current to GND 7 µA ILVDS LVDS Pin Pull-Down Current to GND 7 µA tAP Sample and Hold Acquisition Delay Time 0.4 ns tJITTER Sample and Hold Acquisition Delay Time Jitter 95 fsRMS Full Power Bandwidth Figure 8 Test Circuit 1200 MHz A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) |
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