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AOZ1905DI Datasheet(PDF) 9 Page - Alpha & Omega Semiconductors |
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AOZ1905DI Datasheet(HTML) 9 Page - Alpha & Omega Semiconductors |
9 / 16 page AOZ1905 Rev. 1.5 December 2008 www.aosmd.com Page 9 of 16 quency, input and output voltage. The output ripple volt- age calculation can be simplified to: Output capacitor with the range of 4.7µF to 22µF ceramic capacitor usually can meet most applications. Diode The output rectifier diode freewheels the inductor current to output when the internal MOSFET is off. To reduce losses due to diode forward voltage and reverse recov- ery, Schottky diode is preferred in AOZ1905. The reverse voltage of selected diode should be higher than output voltage, the average current rating should be higher than the maximum load current and the peak current rating should be greater than the peak current of inductor: Loop Compensation The AOZ1905 employs peak current mode control for easy use and fast transient response. Peak current mode control eliminates the double pole effect of the output L&C filter. It greatly simplifies the compensation loop design. With peak current mode control, the boost power stage can be simplified to be a one-pole, one left plane zero and one right half plane (RHP) system in frequency domain. The pole is dominant pole and can be calculated by: The zero is a ESR zero due to output capacitor and its ESR. It is can be calculated by: where; CO is the output filter capacitor, RL is load resistor value, and ESRCO is the equivalent series resistance of output capacitor. The RHP zero has the effect of a zero in the gain causing an imposed +20dB/decade on the roll off, but has the effect of a pole in the phase, subtracting 90° in the phase. The RHP zero can be calculated by: The RHP zero obviously can cause the instable issue if the bandwidth is higher. It is recommended to design the bandwidth to lower than the one half frequency of RHP zero. The compensation design is actually to shape the converter close loop transfer function to get desired gain and phase. Several different types of compensation network can be used for AOZ1905. For most cases, a series capacitor and resistor network connected to the COMP pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. In the AOZ1905, FB pin and COMP pin are the inverting input and the output of internal transconductance error amplifier. A series R and C compensation network con- nected to COMP provides one pole and one zero. The pole is: where; GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, GVEA is the error amplifier voltage gain, which is 340 V/V, and CC is compensation capacitor. The zero given by the external compensation network, capacitor CC (C3 in Figure 1) and resistor RC (R3 in Figure 1), is located at: Choosing the suitable CC and RC by trading-off stability and bandwidth. Thermal Management and Layout Consideration In the AOZ1905 boost regulator circuit, high pulsing current flows through two circuit loops. The first loop starts from the input capacitors, to the filter inductor, to the LX pin, to the internal NMOS switch, to the ground and back to the input capacitor, when the switch turns on. The second loop starts from input capacitor, to the filter inductor, to the LX pin to the external diode, to the ground and back to the input capacitor, when the switch is off. ΔVO IL 1 VIN VOUT --------------- – ⎝⎠ ⎜⎟ ⎛⎞ fCO × ------------------------------ × = ILpeak IIN ΔIL 2 -------- + = fP1 1 2 π C O RL × × ----------------------------------- = fZ1 1 2 π CO ESRCO × × ------------------------------------------------ = fZ2 VIN 2 2 π LIO VO × × × ------------------------------------------- = fP2 GEA 2 π CC GVEA × × ------------------------------------------- = fZ2 1 2 π CC RC × × ----------------------------------- = |
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