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LTC1771IS8 Datasheet(PDF) 10 Page - Linear Technology |
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LTC1771IS8 Datasheet(HTML) 10 Page - Linear Technology |
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10 / 16 page  10 LTC1771 continuous mode, IGATECHG = fQP where QP is the gate charge of the internal switch. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 3. I2R losses are predicted from the internal switch, induc- tor and current sense resistor. In continuous mode the average output current flows through L but is “chopped” between the P-channel MOSFET in series with RSENSE and the output diode. The MOSFET RDS(ON) plus RSENSE multiplied by the duty cycle can be summed with the resistance of L to obtain I2R losses. 4. The catch diode loss is proportional to the forward drop as the diode conducts current during the off-time and is more pronounced at high supply voltages where the off-time is long. However, as discussed in the Catch Diode section, diodes with lower forward drops often have higher leakage currents, so although efficiency is improved, the no-load supply current will increase. The diode loss is calculated by multiplying the forward voltage drop times the diode duty cycle multiplied by the load current. Other losses including CIN and COUT ESR dissipative losses, and inductor core losses, generally account for less than 2% total additional loss. Output Voltage Programming The output voltage is programmed with an external divider from VOUT to VFB (Pin 1) as shown in Figure 2. The regulated voltage is determined by: V R R OUT =+ 123 1 2 1 . To minimize no-load supply current, resistor values in the megohm range should be used. The increase in supply current due to the feedback resistors can be calculated from: ∆= + I V RR V V OUT OUT IN VIN 12 A 5pF feedforward capacitor across R2 is recommended to minimize output voltage ripple in Burst Mode operation. Run/Soft-Start Function The RUN/SS pin is a dual purpose pin that provides the soft- start function and a means to shut down the LTC1771. Soft-start reduces the input surge current from VIN by gradually increasing the internal current limit. Power supply sequencing can also be accomplished using this pin. An internal 1 µA current source charges up an external capacitor CSS. When the voltage on the RUN/SS reaches 1V, the LTC1771 begins operating. As the voltage on the RUN/SS continues to ramp from 1V to 2.2V, the internal current limit is also ramped at a proportional linear rate. The current limits begins near 40% maximum load at VRUN/SS = 1V and ends at maximum load at VRUN/SS = 2.2V. The output current thus ramps up slowly, reducing the starting surge current required from the input power supply. If the RUN/SS has been pulled all the way to ground, there will be a delay before the current limit starts increasing and is given by: tDELAY ≈ CSS/ICHG where ICHG ≅ 1µA. Pulling the RUN/SS pin below 0.5V puts the LTC1771 into a low quiescent current shutdown (IQ < 2µA). Foldback Current Limiting As described in the Catch Diode Selection, the worst-case dissipation for diode occurs with a short-circuit output, when the diode conducts the current limit value almost continuously. In most applications this will not cause excessive heating, even for extended fault intervals. How- ever, when heat sinking is at a premium or higher forward voltage drop diodes are being used, foldback current VFB R2 CFF 5pF R1 VOUT 1771 F02 LTC1771 GND Figure 2. LTC1771 Adjustable Configuaration APPLICATIO S I FOR ATIO |
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