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LTC6906 11 6906fa Performance graphs. VSET changesapproximately–2.3mV/ °C. At room temperature VSET increases 18mV/octave or 60mV/decade of increase in ISET. If the SET pin is driven with a current source generating ISET, the oscillator output frequency will be: ƒOSC SET SET I pF mV n I A mV C ≅ ⎛ ⎝⎜ ⎞ ⎠⎟ ° 10 25 9 82 10 23 18 .• • –. / – Figure 17 and Figure 18 show a current controlled oscilla- tor and a voltage controlled oscillator. These circuits are not highly accurate if used alone, but can be very useful if they are enclosed in an overall feedback circuit such as a phase-locked loop. Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. APPLICATIO S I FOR ATIO Figure 17. Current Controlled Oscillator Figure 18. Voltage Controlled Oscillator V+ GND DIV OUT GRD SET LTC6906 RSET 100 Ω V+ 3.6V TO 5.5V DC 1 µF 6906 F16 Figure 16. Using the LTC6906 at Higher Supply Voltages unpredictable oscillator behavior. Accuracy under higher supplies may be estimated from the typical Frequency vs Supply Voltage curves in the Typical Performance Charac- teristics section of this data sheet. V+ GND DIV OUT GRD SET LTC6906 ICTRL 0.65 µA TO 6.5µA V+ 6906 F17 100kHz TO 1MHz V+ GND DIV OUT GRD SET LTC6906 RSET 100k VCTRL 0V TO 0.585V V+ 6906 F18 1MHz TO 100kHz Alternative Methods for Setting the Output Frequency Any means of sinking current from the SET pin will control the output frequency of the LTC6906. Equation 2 (re- peated below) gives the fundamental relationship between frequency and the SET pin voltage and current: t V I pF OSC OSC SET SET == 1 10 ƒ • (2) This equation shows that the LTC6906 converts conduc- tance (ISET/VSET) to frequency or, equivalently, converts resistance (RSET = VSET/ISET) to period. VSET is the voltage across an internal diode, and as such it is given approximately by: V V Log I I mV Log I A mV C SET T e SET S e SET ≅ ≅ ⎛ ⎝⎜ ⎞ ⎠⎟ ° • .• • –. / – 25 9 82 10 23 18 where VT = kT/q = 25.9mV at T = 300°K (27°C) IS ≅ 82 • 10–18 Amps (IS is also temperature dependent) VSET varies with temperature and the SET pin current. The response of VSET to temperature is shown in the Typical Jitter and Divide Ratio At a given output frequency, a higher master oscillator frequency and a higher divide ratio will result in lower jitter and higher power supply dissipation. Indeterminate jitter percentage will decrease by a factor of slightly less than the square root of the divider ratio, while determinate jitter will not be similarly attenuated. Please consult the speci- fication tables for typical jitter at various divider ratios. |
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