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LTC6906 8 6906fa APPLICATIO S I FOR ATIO Selecting RSET and the Divider Ratio The LTC6906 contains a master oscillator followed by a digital divider (see Block Diagram). RSET determines the master oscillator frequency and the DIV pin sets the divider ratio, N. The range of frequencies accessible in each divider ratio overlap, as shown in Figure 7. This figure is derived from the equations in Table 1. For any given frequency, power can be minimized by minimiz- ing the master oscillator frequency. This implies maxi- mizing RSET and using the lowest possible divider ratio, N. The relationship between RSET, N and the unloaded power consumption is shown in Figure 8, where we can clearly see that supply current decreases for large values of RSET. For a discussion of jitter and divide ratio, refer to page 11. Minimizing Power Consumption The supply current of the LTC6906 has four current components: • Constant (Independent V+, ƒOUT and CLOAD) • Proportional to ISET (which is the current in RSET) • Proportional to V+, ƒOUT and CLOAD • Proportional to V+ and RLOAD An approximate expression for the total supply current is: IA I V C pF V R A V R VC pF V R SET OUT LOAD LOAD SET SET OUT LOAD LOAD ++ + + + ≅ µ+ + + ()+ ≅ µ+ + + ()+ 56 5 2 56 5 2 •• • • •• • • ƒ ƒ VSET is approximately 650mV at 25°C, but varies with temperature. This behavior is shown in the Typical Perfor- mance Characteristics. Power can be minimized by maximizing RSET, minimizing the load on the OUT pin and operating at lower frequen- cies. Figure 9 shows total supply current vs frequency Figure 7. RSET vs Desired Output Frequency (LTC6906) Figure 8. Unloaded Supply Current vs RSET RSET (kΩ) 50 70 100 1000 6906 F09 30 40 60 80 20 10 0 CLOAD = 0 V+ = 3V TA = 25°C under typical conditions. Below 100kHz the load current is negligible for the 5pF load shown. Guarding Against PC Board Leakage The LTC6906 uses relatively large resistance values for RSET to minimize power consumption. For RSET = 1M, the SET pin current is typically only 6.5 µA. Thus, only 6.5nA leaking into the SET pin causes a 0.1% frequency error. Similarly, 1G of leakage resistance across RSET (1000 • RSET) causes the same 0.1% error. OUTPUT FREQUENCY (kHz) 1000 10000 1 100 1000 10000 6906 F07 10 10 100 ÷10 ÷3 ÷1 |
