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LTC1750 Datasheet(PDF) 9 Page - Linear Technology |
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LTC1750 Datasheet(HTML) 9 Page - Linear Technology |
9 / 20 page 9 LTC1750 1750f PI FU CTIO S SENSE (Pin 1): Reference Sense Pin. GND selects a VREF of 0.7V. VDD selects 1.125V. When VSENSE is between 0.7V and 1.125V, VSENSE is used as VREF. The ADC input range is ±VREF/PGA gain. VCM (Pin 2): 2.0V Output and Input Common Mode Bias. Bypass to ground with 4.7 µF ceramic chip capacitor. GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): ADC Power Ground. AIN+ (Pin 4): Positive Differential Analog Input. AIN– (Pin 5): Negative Differential Analog Input. VDD (Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to AGND with 1 µF ceramic chip capacitors at Pin 8 and Pin 18. REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11 with 0.1 µF ceramic chip capacitor. Do not connect to Pin 14. REFHA (Pin 11): ADC High Reference. Bypass to Pin 10 with 0.1 µFceramicchipcapacitor,toPin14witha4.7µFceramic capacitor and to ground with 1 µF ceramic capacitor. REFLA (Pin 14): ADC Low Reference. Bypass to Pin 15 with 0.1 µF ceramic chip capacitor, to Pin 11 with a 4.7µF ce- ramic capacitor and to ground with 1 µF ceramic capacitor. REFHB (Pin 15): ADC High Reference. Bypass to Pin 14 with 0.1 µF ceramic chip capacitor. Do not connect to Pin 11. MSBINV (Pin 22): MSB Inversion Control. Low inverts the MSB, 2’s complement output format. High does not invert the MSB, offset binary output format. ENC (Pin 23): Encode Input. The input sample starts on the positive edge. ENC (Pin 24): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1 µF ceramic for single-ended ENCODE signal. PGA (Pin 25): Programmable Gain Amplifier Control. Low selects an effective front-end gain of 1. High selects an effective gain of 1 2/3. The ADC input range is ±VREF/PGA gain. CLKOUT (Pin 26): Data Valid Output. Latch data on the rising edge of CLKOUT. OGND (Pins 27, 38, 47): Output Driver Ground. D0-D3 (Pins 28 to 31): Digital Outputs. OVDD (Pins 32, 43): Positive Supply for the Output Driv- ers. Bypass to ground with 0.1 µF ceramic chip capacitor. D4-D6 (Pins 33 to 35): Digital Outputs. D7-D10 (Pins 39 to 42): Digital Outputs. D11-D13 (Pins 44 to 46): Digital Outputs. OF (Pin 48): Over/Under Flow Output. High when an over or under flow has occurred. |
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