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LTC6404 17 6404f PIN FUNCTIONS potential. On the LTC6404-2, the VOCM pin has a input resistance of approximately 14k. On the LTC6404-4, the VOCM pin has a input resistance of approximately 7k. The VOCM pin should be bypassed with a high quality ceramic bypass capacitor of at least 0.01μF, (unless you are using split supplies, then connect directly to a low impedance, low noise ground plane) to minimize common mode noise from being converted to differential noise by impedance mismatches both externally and internally to the IC. NC (Pins 5, 16): No Connection. These pins are not con- nected internally. OUT+, OUT– (Pins 7, 14): Unfiltered Output Pins. Besides driving the feedback network, each pin can drive an ad- ditional 50 Ω to ground with typical short-circuit current limiting of ±65mA. Each amplifier output is designed to drive a load capacitance of 10pF. This basically means the amplifier can drive 10pF from each output to ground or 5pF differentially. Larger capacitive loads should be decoupled with at least 25 Ω resistors in series with each output. For long-term device reliability, it is recommended that the continuous (DC + ACRMS) output current be limited to under 50mA. OUTF+, OUTF– (Pins 8, 13): Filtered Output Pins. These pins have a series 50 Ω resistor connected between the filtered and unfiltered outputs and three 12pF capacitors. Both OUTF+ and OUTF– have 12pF to V–, plus an additional 12pF differentially between OUTF+ and OUTF–. This filter creates a differential lowpass frequency response with a –3dB bandwidth of 88.5MHz. For long-term device reliability, it is recommended that the continuous (DC + ACRMS) output current be limited to under 40mA. IN+, IN– (Pins 15, 6): Noninverting and Inverting Input Pins of the Amplifier, Respectively. For best performance, it is highly recommended that stray capacitance be kept to an absolute minimum by keeping printed circuit connections as short as possible, and if necessary, stripping back nearby surrounding ground plane away from these pins. Exposed Pad (Pin 17): Tie the pad to V– (Pins 3, 9, and 12). If split supplies are used, do not tie the pad to ground. BLOCK DIAGRAM – + 1 5 NC 6 IN– 7 OUT+ 8 OUTF+ 16 NC 15 IN+ 14 OUT– 13 OUTF– 2 V+ 3 V– V+ V+ V+ V+ V+ V– V– V+ V+ 50Ω 12pF 12pF 12pF 66k V– 4 VOCM VOCM 12 V– 6404 BD 11 V+ 10 V+ 9 V– 50Ω 2 • RVOCM 2 • RVOCM V– V– V+ V– V+ V– V+ V– V+ V– V+ V– V– V– SHDN IC LTC6404-1 LTC6404-2 LTC6404-4 2 • RVOCM 47k 28k 14k |
