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LTC4442EMS8E-PBF Datasheet(PDF) 9 Page - Linear Technology |
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LTC4442EMS8E-PBF Datasheet(HTML) 9 Page - Linear Technology |
9 / 12 page LTC4442/LTC4442-1 9 4442fa APPLICATIONS INFORMATION The LTC4442’s powerful parallel combination of the N-channel MOSFET (N2) and NPN (Q3) on the BG pull-down generates a phenomenal 5ns fall time on BG while driving a 3nF load. Similarly, the 1Ω pull-down MOSFET (N1) on TG results in a rapid 8ns fall time with a 3nF load. These powerful pull-down devices minimize the power loss as- sociated with MOSFET turn-off time and cross-conduction current. OPERATION Power Dissipation To ensure proper operation and long-term reliability, the LTC4442 must not operate beyond its maximum tem- perature rating. Package junction temperature can be calculated by: TJ = TA + (PD)(θJA) where: TJ = Junction temperature TA = Ambient temperature PD = Power dissipation θJA = Junction-to-ambient thermal resistance Power dissipation consists of standby, switching and capacitive load power losses: PD = PDC + PAC + PQG where: PDC = Quiescent power loss PAC = Internal switching loss at input frequency fIN PQG = Loss due turning on and off the external MOSFET with gate charge QG at frequency fIN The LTC4442 consumes very little quiescent current. The DC power loss at VLOGIC = 5V and VCC = VBOOST − TS = 7V is only (730μA)(5V) + (625μA)(7V) = 8mW. At a particular switching frequency, the internal power loss increases due to both AC currents required to charge and discharge internal nodal capacitances and cross-conduc- tion currents in the internal logic gates. The sum of the quiescent current and internal switching current with no load are shown in the Typical Performance Characteristics plot of Switching Supply Current vs Input Frequency. The gate charge losses are primarily due to the large AC currents required to charge and discharge the capacitance of the external MOSFETs during switching. For identical pure capacitive loads CLOAD on TG and BG at switching frequency fin, the load losses would be: PCLOAD = (CLOAD)(fIN)[(VBOOST – TS)2 + (VCC)2] In a typical synchronous buck configuration, VBOOST – TS is equal to VCC – VD, where VD is the forward voltage drop across the diode between VCC and BOOST. If this drop is small relative to VCC, the load losses can be approximated as: PCLOAD ≈ 2(CLOAD)(fIN)(VCC)2 Unlike a pure capacitive load, a power MOSFET’s gate capacitance seen by the driver output varies with its VGS voltage level during switching. A MOSFET’s capacitive load power dissipation can be calculated using its gate charge, QG. The QG value corresponding to the MOSFET’s VGS value (VCC in this case) can be readily obtained from the manufacturer’s QG vs VGS curves. For identical MOSFETs on TG and BG: PQG ≈ 2(VCC)(QG)(fIN) To avoid damaging junction temperatures due to power dissipation, the LTC4442 includes a temperature monitor that will pull BG and TG low if the junction temperature exceeds 160°C. Normal operation will resume when the junction temperature cools to less than 135°C. Bypassing and Grounding The LTC4442 requires proper bypassing on the VLOGIC, VCC and VBOOST – TS supplies due to its high speed switching (nanoseconds) and large AC currents (Amperes). Careless component placement and PCB trace routing may cause excessive ringing and undershoot/overshoot. |
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