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LTC4306CGN Datasheet(PDF) 10 Page - Linear Technology |
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LTC4306CGN Datasheet(HTML) 10 Page - Linear Technology |
10 / 20 page LTC4306 4306f 10 The LTC4306 is a 4-channel, 2-wire bus multiplexer/ switch with bus buffers to provide capacitive isolation between the upstream bus and downstream buses. Mas- ters on the upstream 2-wire bus (SDAIN and SCLIN) can command the LTC4306 to any combination of the 4 downstream buses. Masters can also program the LTC4306 to disconnect the upstream bus from the downstream buses if the bus is stuck low. Undervoltage Lockout (UVLO) and ENABLE Functionality The LTC4306 contains undervoltage lockout circuitry that maintains all of its SDA, SCL, GPIO and ALERT pins in high impedance states until the device has sufficient VCC supply voltage to function properly. It also ignores any attempts to communicate with it via the 2-wire buses in this condi- tion. When the ENABLE pin voltage is low (below 0.8V), all control bits are reset to their default high impedance states, and the LTC4306 ignores 2-wire bus commands. However, with ENABLE low, the LTC4306 still monitors the ALERT1-ALERT4 pin voltages and pulls the ALERT pin low if any of ALERT1-ALERT4 is low. When ENABLE is high, devices can read from and write to the LTC4306. Connection Circuitry Masters on the upstream SDAIN/SCLIN bus can write to the Bus 1 FET State through Bus 4 FET State bits of register 3 to connect to any combination of downstream channels 1 to 4. By default, the Connection Circuitry shown in the Block Diagram will only connect to downstream channels whose corresponding Bus Logic State bits in register 3 are high at the moment that it receives the connection com- mand. If the LTC4306 is commanded to connect to mul- tiple channels at once, it will only connect to the channels that are high. Masters can override this feature by setting the Connection Requirement bit of register 2 high. With this bit high, the LTC4306 executes connection com- mands without regard to the logic states of the down- stream channels. Upon receiving the connection command, the Connec- tion Circuitry will activate the Upstream-Downstream Buffers under two conditions: first, the master must be commanding connection to one or more downstream channels, and second, there must be no stuck low condition (see Stuck Low Timeout Fault discussion). If the connection command is successful, the Upstream- Downstream Buffers pass signals between the upstream bus and the connected downstream buses. The LTC4306 also turns off its N-channel MOSFET open-drain pull- down on the READY pin, so that READY can be pulled high by its external pull-up resistor. Upstream-Downstream Buffers Once the Upstream-Downstream Buffers are activated, the functionality of the SDAIN and any connected down- stream SDA pins is identical. A low forced on any con- nected SDA pin at any time results in all pins being low. External devices must pull the pin voltages below 0.4V worst-case with respect to the LTC4306’s ground pin to ensure proper operation. The SDA pins enter a logic high state only when all devices on all connected SDA pins force a high. The same is true for SCLIN and the connected downstream SCL pins. This important feature ensures that clock stretching, clock arbitration and the acknowl- edge protocol always work, regardless of how the devices in the system are connected to the LTC4306. The Upstream-Downstream Buffers provide capacitive isolation between SDAIN/SCLIN and the downstream con- nected buses. Note that there is no capacitive isolation between connected downstream buses; they are only separated by the series combination of their switches’ on resistances. While any combination of downstream buses may be connected at the same time, logic high levels are corrupted if multiple downstream buses are active and both the VCC voltage and one or more downstream bus pull-up voltages are larger than the pull-up supply voltage for another downsteam bus. An example of this issue is shown in Figure 1. During logic highs, DC current flows from VBUS1 through the series combination of R1, N1, N2 and R2 and into VBUS2, causing the SDA1 voltage to drop and current to be sourced into VBUS2. To avoid this problem, do not activate bus 1 or any other downstream bus whose pull- up voltage is above 2.5V when bus 2 is active. OPERATIO |
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