9

LTC1662

Alternatively, one DAC may be loaded with a new input

code during Sleep; then with just one command, the other

DAC is loaded, the part is awakened and both outputs are

updated.

wakes the part and simultaneously updates both DAC

outputs.

Voltage Outputs

Each of the rail-to-rail output amplifiers contained in the

LTC1662 can typically source or sink at least 1mA

of either supply when unloaded and have an equivalent

output resistance of 130

Ω (typical) when driving a load

to the rails. The output amplifiers are stable driving

capacitive loads of up to 1000pF.

A small resistor placed in series with the output can be

used to achieve stability for any load capacitance. Please

see the Output Minimum Resistance vs Load Capaci-

tance curve in the Typical Performance Characteristics

section.

Rail-to-Rail Output Considerations

In any rail-to-rail DAC, the output swing is limited to

voltages within the supply range.

If the DAC offset is negative, the output for the lowest

codes limits at 0V as shown in Figure 2b.

Similarly, limiting can occur near full scale when the REF

Offset and linearity are defined and tested over the region

of the DAC transfer function where no output limiting can

occur.

The first of these, the Input Register, is used for loading new

input codes. The second buffer, the DAC Register, is used

for updating the DAC outputs. Each DAC has its own 10-bit

Input Register and 10-bit DAC Register.

By selecting the appropriate 4-bit Control code (see Table 1)

it is possible to perform single operations, such as loading

one DAC or changing Power-Down status (Sleep/Wake).

In addition, some Control codes perform two or more

operations at the same time. For example, one such code

loads DAC A, updates both outputs and Wakes the part up.

The DACs can be loaded separately or together, but the

outputs are always updated together.

Register Loading Sequence

See Figure 1. With CS/LD held low, data on the SDI input

is shifted into the 16-bit Shift Register on the positive edge

of SCK. The 4-bit Control code, A3-A0, is loaded first, then

the 10-bit Input code, D9-D0, ordered MSB-to-LSB in each

case. Two don’t-care bits, X1 and X0, are loaded last.

When the full 16-bit Input word has been shifted in, CS/LD

is pulled high, causing the system to respond according to

Table 1. The clock is disabled internally when CS/LD is

high. Note: SCK must be low when CS/LD is pulled low.

Sleep Mode

instruction (see Table 1). In this mode, static power

consumption is greatly reduced. The reference input and

analog outputs are set in a high impedance state and all

DAC settings are retained in memory so that when Sleep

mode is exited, the outputs of DACs not updated by the

Wake command are restored to their last active state.

Sleep mode is initiated by performing a load sequence

ignored).

To save instruction cycles, the DACs may be prepared with

to wake the part and to update the output values.

OPERATIO