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LTC1659CMS8-TRPBF Datasheet(PDF) 7 Page - Linear Technology |
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LTC1659CMS8-TRPBF Datasheet(HTML) 7 Page - Linear Technology |
7 / 12 page LTC1659 7 1659fa TIMING DIAGRAM DEFINITIONS B11 MSB B10 t1 t9 B1 t6 B0 LSB B11 CURRENT WORD t7 t2 t4 t3 t8 CLK DIN DOUT CS/LD t5 1659 TD B0 PREVIOUS WORD B11 PREVIOUS WORD B10 B1 B0 Differential Nonlinearity (DNL): The difference between the measured change and the ideal 1LSB change for any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = ( ΔVOUT – LSB)/LSB where ΔVOUT is the measured voltage difference between two adjacent codes. Digital Feedthrough: The glitch that appears at the ana- log output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec). Full-Scale Error (FSE): The deviation of the actual full-scale voltage from ideal. FSE includes the effects of offset and gain errors (see Applications Information). Integral Nonlinearity (INL): The deviation from a straight line passing through the endpoints of the DAC transfer curve (Endpoint INL). Because the output cannot go below zero, the linearity is measured between full scale and the lowest code which guarantees the output will be greater than zero. The INL error at a given input code is calculated as follows: INL = [VOUT – VOS – (VFS – VOS)(code/4095)]/LSB where VOUT is the output voltage of the DAC measured at the given input code. Least Significant Bit (LSB): The ideal voltage difference between two successive codes. LSB = VREF/4096 Resolution (n): Defines the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Voltage Offset Error (VOS): Nominally, the voltage at the output when the DAC is loaded with all zeros. A single supply DAC can have a true negative offset, but the output cannot go below zero (see Applications Information). For this reason, single supply DAC offset is measured at the lowest code that guarantees the output will be greater than zero. |
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