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LTC1266AIS Datasheet(PDF) 10 Page - Linear Technology |
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LTC1266AIS Datasheet(HTML) 10 Page - Linear Technology |
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10 / 20 page  10 LTC1266 LTC1266-3.3/LTC1266-5 current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple which can cause Burst Mode operation to be falsely triggered. Do not allow the core to saturate! Kool M µis a very good, low loss core material for toroids, with a “soft” saturation characteristic. Molypermalloy is slightly more efficient at high (> 200kHz) switching fre- quency. Toroids are very space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. However, new designs for surface mount are available from Coiltronics and Beckman Industrial Corp. which do not increase the height significantly. Power MOSFET and D1 Selection Two external power MOSFETs must be selected for use with the LTC1266 series: either a P-channel MOSFET or an N-channel MOSFET for the main switch and an N-channel MOSFET for the synchronous switch. The main selection criteria for the power MOSFETs are the type of MOSFET, threshold voltage VGS(TH) and on-resistance RDS(ON). The cost and maximum output current determine the type of MOSFET for the topside switch. N-channel MOSFETs have the advantage of lower cost and lower RDS(ON) at the expense of slightly increased circuit complexity. For lower current applications where the losses due to RDS(ON) are small, a P-channel MOSFET is recommended due to the lower circuit complexity. However, at load currents in excess of 3A where the RDS(ON) becomes a significant portion of the total power loss, an N-channel is strongly recommended to maximize efficiency. The maximum output current IMAX determines the RDS(ON) requirement for the two MOSFETs. When the LTC1266 series is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the average load current. The duty cycles for the two MOSFETs are given by: Topside Duty Cycle = VOUT VIN Bottom-Side Duty Cycle = VIN – VOUT VIN As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The complete expression for operating frequency of the circuit in Figure 1 is given by: f = 1 tOFF ) )1– VOUT VIN where: tOFF = 1.3 • 104 • CT • ) )VREG VOUT VREG is the desired output voltage (i.e., 5V, 3.3V). VOUT is the measured output voltage. Thus VREG/VOUT = 1 in regulation. Once the frequency has been set by CT, the inductor L must be chosen to provide no more than 25mV/RSENSE of peak-to-peak inductor ripple current. This results in a minimum required inductor value of: LMIN = 5.1 • 105 • RSENSE • CT • VREG As the inductor value is increased from the minimum value, the ESR requirements for the output capacitor are eased at the expense of efficiency. If too small an inductor is used, the inductor current will decrease past zero and change polarity. A consequence of this is that the LTC1266 series may not enter Burst Mode operation and efficiency will be slightly degraded at low currents. Inductor Core Selection Once the minimum value for L is known, the type of inductor must be selected. The highest efficiency will be obtained using ferrite, Kool M µ® on molypermalloy (MPP) cores. Lower cost powdered iron cores provide suitable performance but cut efficiency by 3% to 7%. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As induc- tance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses increase. Ferrite designs have very low core loss, so design goals can concentrate on copper loss and preventing satura- tion. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design Kool M µ is a registered trademark of Magnetics, Inc. APPLICATIO S I FOR ATIO |
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