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A3P060-FPQ144PP Datasheet(PDF) 1 Page - Actel Corporation

Part # A3P060-FPQ144PP
Description  ProASIC3 Flash Family FPGAs
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

A3P060-FPQ144PP Datasheet(HTML) 1 Page - Actel Corporation

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February 2008
I
© 2008 Actel Corporation
ProASIC3 Flash Family FPGAs
with Optional Soft ARM® Support
Features and Benefits
High Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except ARM-enabled ProASIC®3
devices) via JTAG (IEEE 1532–compliant)†
•FlashLock® to Secure FPGA Contents
Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended
I/O
Standards:
LVTTL,
LVCMOS
3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
• Programmable Output Slew Rate† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL
• Configurable
Phase-Shift,
Multiply/Divide,
Delay
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
• True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
• M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft
Processor Available with or without Debug
®
† A3P015 and A3P030 devices do not support this feature.
‡ Supported only by A3P015 and A3P030 devices.
ProASIC3 Product Family
ProASIC3 Devices
A3P015
A3P030
A3P060
A3P125
A3P250
A3P400
A3P600
A3P1000
ARM7 Devices 1
M7A3P1000
Cortex-M1 Devices 1
M1A3P250
M1A3P400
M1A3P600
M1A3P1000
System Gates
15 k
30 k
60 k
125 k
250 k
400 k
600 k
1 M
Typical Equivalent Macrocells
128
256
512
1,024
VersaTiles (D-flip-flops)
384
768
1,536
3,072
6,144
9,216
13,824
24,576
RAM kbits (1,024 bits)
18
36
36
54
108
144
4,608-Bit Blocks
4
8
8
122432
FlashROM Bits
1 k
1 k
1 k
1 k
1 k
1 k
1 k
1 k
Secure (AES) ISP 2
Yes
Yes
Yes
Yes
Yes
Yes
Integrated PLL in CCCs
––
1
1
1
1
1
1
VersaNet Globals 3
6
6
18
18
18
18
18
18
I/O Banks
22
2
2
4
4
4
4
Maximum User I/Os
49
81
96
133
157
194
235
300
Package Pins
QFN
VQFP
TQFP
PQFP
FBGA
QN68
QN132
VQ100
QN132
VQ100
TQ144
FG144
QN132
VQ100
TQ144
PQ208
FG144
QN132 5
VQ100
PQ208
FG144/256 5
PQ208
FG144/256/
484
PQ208
FG144/256/
484
PQ208
FG144/256/
484
Notes:
1. Refer to the CoreMP7 datasheet or Cortex-M1 product brief for more information.
2. AES is not available for ARM-enabled ProASIC3 devices.
3. Six chip (main) and three quadrant global networks are available for A3P060 and above.
4. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs handbook.
5. The M1A3P250 device does not support this package.
v1.0


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