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RTAX2000-SLCG624EV Datasheet(PDF) 9 Page - Actel Corporation |
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RTAX2000-SLCG624EV Datasheet(HTML) 9 Page - Actel Corporation |
9 / 170 page RTAX-S/SL RadTolerant FPGAs v5.3 1-1 General Description RTAX-S/SL offers high performance at densities of up to two million equivalent system gates for space-based applications. Based upon the Actel commercial Axcelerator® family, RTAX-S/SL has several system-level features such as embedded SRAM (with built-in FIFO control logic), segmentable clocks, chip-wide highway routing, and carry logic. Featuring SEU-hardened flip-flops that offer the benefits of user-implemented Triple Module Redundancy (TMR) without the associated overhead, the RTAX-S/SL family is the second generation Actel product offering for space applications. The RTAX-S/SL devices are manufactured using a 0.15 µm technology at a UMC facility in Taiwan. These devices offer levels of radiation survivability far in excess of typical CMOS devices. Device Architecture Actel RTAX-S/SL architecture, derived from the highly- successful A54SX-A sea-of-modules architecture, has been designed for high performance and total logic module utilization (Figure 1-1). Unlike traditional FPGAs, the entire floor of the RTAX-S/SL device is covered with a grid of logic modules, with virtually no chip area lost to interconnect elements or routing. Programmable Interconnect Element The RTAX-S/SL family uses a patented metal-to-metal antifuse programmable interconnect element that resides between the upper two layers of metal (Figure 1-2 on page 1-2). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on traditional FPGAs) and enables the efficient sea-of-modules architecture. The antifuses are normally open circuit and, when programmed, form a permanent, passive, low- impedance connection, leading to the fastest signal propagation in the industry. In addition, the extremely small size of these interconnect elements gives the RTAX-S family abundant routing resources. Figure 1-1 • Sea-of-Modules Comparison Switch Matrix Routing Logic Block Logic Modules Sea-of-Modules Architecture Traditional FPGA Architecture |
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