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APA300-FG896A Datasheet(PDF) 3 Page - Actel Corporation |
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APA300-FG896A Datasheet(HTML) 3 Page - Actel Corporation |
3 / 10 page Automotive-Grade ProASICPLUS Flash Family FPGAs A u t o m o t i ve S upp l e m e nt 3 General Description ProASICPLUS devices offer a reprogrammable design integration solution at the automotive temperature range (-40°C to +125°C) through the use of nonvolatile Flash technology. ProASICPLUS devices have a fine-grain architecture, similar to ASICs, and enable engineers to design high-density systems using existing ASIC or FPGA design flows and tools. Automotive-grade ProASICPLUS devices offer up to 1 million system gates, support up to 198kbits of two-port SRAM and 642 user I/Os and provide 50 MHz PCI performance. The nonvolatile and reprogrammable Flash technology enables ProASICPLUS devices to be live at power-up, and no external boot PROM is required to support device programming. While on-board security mechanisms prevent any access to the programmed information, reprogramming can be performed in-system to support future design iterations and field upgrades. The ProASICPLUS device architecture mitigates the complexity of ASIC migration at higher user volume, making the automotive-grade ProASICPLUS a cost-effective solution for in-cabin telematics and automobile interconnect applications. The ProASICPLUS family is built on an advanced Flash- based 0.22 µm LVCMOS process with four layers of metal. Standard CMOS design techniques are used to implement logic and control functions, including the PLLs and LVPECL inputs, resulting in predictable performance fully compatible with gate arrays. The ProASICPLUS architecture provides granularity comparable to gate arrays. The device core consists of a Sea-of-Tiles . Each tile can be configured as a flip-flop, latch, or three-input/one-output logic function by programming the appropriate Flash switches. The combination of fine granularity, flexible routing resources, and abundant Flash switches allows 100% utilization and over 95% routability for highly congested designs. Tiles and larger functions are interconnected through a four-level routing hierarchy. Automotive-grade ProASICPLUS devices feature embedded two-port SRAM blocks with built-in FIFO/RAM control logic and user-defined depth and width. Users can select programming for synchronous or asynchronous operation, as well as parity generation or checking. The automotive-grade ProASICPLUS devices offer a unique clock conditioning circuit (CCC), with two clock conditioning blocks in each device. Each block provides a phase-locked loop (PLL) core, delay lines, phase shifts (0 °, 90 °, 180°, 270°), and clock multipliers/dividers, as well as the circuitry required to provide bidirectional access to the PLL. The PLL block contains four programmable frequency dividers, which allow the incoming clock signal to be divided by a wide range of factors from 1 to 64. The clock conditioning circuit can perform a positive/ negative clock delay operation in increments of 0.25 ns by up to 8 ns. The PLL can be configured internally or externally during operation without redesigning or reprogramming the part. In addition to the PLL, there are two LVPECL differential input pairs to accommodate high speed clock and data inputs. The automotive-grade ProASICPLUS devices are available in a variety of high-performance plastic packages to simplify the system board design. To support for comprehensive, lower cost board-level testing, Actel’s ProASICPLUS devices are fully compatible with IEEE Standard 1149.1 for test access port and boundary-scan test architecture. |
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