HOST READ OPERATION

The host read operation is best described with the diagram in Figure 8 below:

Figure 8: Host Read Logic

Notice in Figure 8 that DATA_VLD can act as the write enable for a register to capture the byte on DATA_OUT for use by the host interface.

PERFORMING TWSI TRANSACTIONS

Single Read

To generate a single read cycle, the address input (ADDR_IN) is written with the desired address and the command input (TWSI_CMD) is written with “011” (binary

011, REPEATED START=0, STOP=1, READ=1) and START is strobed for one clock cycle to perform the operation and stop. When the operation is completed the

DATA_VLD pin will go active and the data may be read on the DATA_OUT port. The user should poll the STATUS pins and restart the operation if necessary if BUS-

LOSS is asserted or attempt another address if SLAVE_TIMEOUT is asserted.

Single Write

To generate a single write cycle:

• The address input (ADDR_IN) is written with the desired address

• The data input (DATA_IN) is written with the byte to be sent

• The command input (TWSI_CMD) is written with “010” (binary 010, REPEATED START=0, STOP=1, READ=0)

• START is strobed for one clock cycle to perform the operation and stop.

When the operation is completed the REQ_DATA pin will go active to ask the host for another byte of data to send. Since this is a single write, REQ_DATA can be

ignored. The user should poll the STATUS pins and restart the operation if necessary if BUSLOSS is asserted or attempt another address if SLAVE_TIMEOUT is

asserted.

Burst Read

A burst read operation is performed in the same manner as a single read, except that the command input (TWSI_CMD) is written with the STOP bit de-asserted

(binary 001). At the end of each byte read the DATA_VLD pin will be asserted. This tells the host that valid data is available on the DATA_OUT port and that START

needs to be strobed for the burst to continue. No new command should be written to the command input while a burst is in process. When the host is done reading

data it will issue the Single Read command (binary 011) and the core will do one more read and stop. Note that there is only one address cycle for a burst read cycle.

In addition, it is not permitted to follow a read operation or burst read operation with a write operation without first performing a repeated start or a stop. The user

should poll the STATUS pins and restart the operation if necessary if BUSLOSS is asserted or attempt another address if SLAVE_TIMEOUT is asserted.

Burst Write

A burst write operation is performed in the same manner as a single write, except that the command input (TWSI_CMD) is written with the STOP bit de-asserted

(binary 001). At the end of each byte written the REQ_DATA pin will be asserted. This tells the host that data is needed on the DATA_IN port and that START needs

to be strobed for the burst to continue. No new command should be written to the command input while a burst is in process. When the host is done writing data it will

issue the Single Write command (binary 010) and the core will do one more write and stop. Note that there is only one address cycle for a burst read cycle. In addi-

tion, it is not permitted to follow a write operation or burst write operation with a read operation without first performing a repeated start or a stop. The user should poll

the STATUS pins and restart the operation if necessary if BUSLOSS is asserted or attempt another address if SLAVE_TIMEOUT is asserted.

Repeated Start

The repeated start operation is used to directly follow a read with a write, or a write with a read, without a stop in-between. Some devices require this for the genera-

tion of a second address; the address within the device as opposed to on the serial bus itself.

Any read or write operation may be followed by a repeated start by resetting the STOP bit and setting the REPEATED START bit when writing to the command input.

For example, to perform a write cycle followed by a repeated start and a read, the command input is written with “100” to perform the write operation. The REQ_DATA

pin will be asserted, as always, at the end of the write. If a single read is then desired the command input is written with “011”.

Fast Mode

For Fast mode of operation, it may be beneficial to filter out glitches on the SDA and SCL inputs. The filter enable bit in the configuration vector (CFG[46]), when high,

will filter out any transition on either SDA or SCL which is less than one clock period wide.

If using Fast mode of operation with very short HI_COUNT and LO_COUNT dividers, it may also be useful to set the “extrahold” bit in the configuration vector

(CFG[47]) high to provide two extra CLK periods of hold time on SDA from the falling edge of SCL.

MDS2106

CLK

DATA_OUT[7:0]

DATA_VLD

Valid