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RT3PE3000L-LG484B Datasheet(PDF) 1 Page - Actel Corporation |
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RT3PE3000L-LG484B Datasheet(HTML) 1 Page - Actel Corporation |
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1 / 144 page  September 2008 I © 2008 Actel Corporation Radiation-Tolerant ProASIC3 Low-Power Space- Flight Flash FPGAs with Flash*Freeze Technology Features and Benefits MIL-STD-883 Class B Qualified Packaging • Ceramic Column Grid Array with Six Sigma Copper- Wrapped Lead-Tin Columns • Land Grid Array Low Power • Dramatic Reduction in Dynamic and Static Power • 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power • Low Power Consumption in Flash*Freeze Mode Enables Instantaneous Entry To / Exit From Low-Power Flash*Freeze Mode • Supports Single-Voltage System Operation • Low-Impedance Switches Radiation Tolerant • 15 krad Total Ionizing Dose (TID) • Wafer-Lot-Specific TID Reports High Capacity • 600 k to 3 M System Gates • Up to 504 kbits of True Dual-Port SRAM • Up to 620 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process • Live-at-Power-Up (LAPU) Level 0 Support • Single-Chip Solution • Retains Programmed Design when Powered Off High Performance • 350 MHz (1.5 V) and 250 MHz (1.2 V) System Performance • 3.3 V, 66 MHz, 66-Bit PCI (1.5 V); 66 MHz, 32-Bit PCI (1.2 V) In-System Programming (ISP) and Security • Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant) •FlashLock® to Secure FPGA Contents High-Performance Routing Hierarchy • Segmented, Hierarchical Routing and Clock Structure • High-Performance, Low-Skew Global Network • Architecture Supports Ultra-High Utilization Advanced and Pro (Professional) I/Os • 700 Mbps DDR, LVDS-Capable I/Os • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 8 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input • Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS • Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II (RT3PE3000L only) • I/O Registers on Input, Output, and Enable Paths • Hot-Swappable and Cold-Sparing I/Os • Programmable Output Slew Rate and Drive Strength • Programmable Input Delay (RT3PE3000L only) • Schmitt Trigger Option on Single-Ended Inputs (RT3PE3000L) • Weak Pull-Up/-Down • IEEE 1149.1 (JTAG) Boundary Scan Test • Pin-Compatible Packages across the Radiation-Tolerant ProASIC®3 Family Clock Conditioning Circuit (CCC) and PLL • Six CCC Blocks, All with Integrated PLL (RT ProASIC3) • Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback • Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V systems) and 350 MHz (1.5 V systems) SRAMs and FIFOs • Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available) • True Dual-Port SRAM (except ×18) • 24 SRAM and FIFO Blocks with Synchronous Operation: – 250 MHz: For 1.2 V Systems – 350 MHz: For 1.5 V Systems ® Table I-1 • Radiation-Tolerant (RT) ProASIC3 Low-Power Space-Flight FPGAs RT ProASIC3 Devices RT3PE600L RT3PE3000L System Gates 600 k 3 M VersaTiles (D-flip-flops) 13,824 75,264 RAM kbits (1,024 bits) 108 504 4,608-Bit Blocks 24 112 FlashROM Bits 1 k 1 k Secure (AES) ISP Yes Yes Integrated PLL in CCCs 66 VersaNet Globals 18 18 I/O Banks 88 Maximum User I/Os 270 620 Package Pins CCGA/LGA CG/LG484 CG/LG484, CG/LG896 Advance v0.1 |
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