PROASIC3E datasheet(8/37 Pages) ACTEL

Part #	PROASIC3E

Description	I/O Structures in IGLOOe and ProASIC3E Devices

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Manufacturer	ACTEL [Actel Corporation]

Direct Link	http://www.actel.com

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I/O Structures in IGLOOe and ProASIC3E Devices

8v1.4

I/O Architecture

I/O Tile

The I/O tile provides a flexible, programmable structure for implementing a large number of I/O

standards. In addition, the registers available in the I/O tile can be used to support high-

performance register inputs and outputs, with register enable if desired (Figure 3). The registers

can also be used to support the JESD-79C Double Data Rate (DDR) standard within the I/O structure

(see DDR for Actel’s Low-Power Flash Devices for more information).

As depicted in Figure 3, all I/O registers share one CLR port. The output register and output enable

register share one CLK port.

Figure 3 • I/O Block Logical Representation

Input

Register

E = Enable Pin

A

Y

PAD

1

2

3

4

5

6

OCE

ICE

Input

Register

Input

Register

CLR/PRE

Pull-Up/-Down

Resistor Control

Signal Drive Strength

and Slew Rate Control

Output

Register

Output

Register

To FPGA Core

From FPGA Core

Output

Enable

Register

OCE

I/O / CLR or I/O / PRE / OCE

I/O / Q0

I/O / Q1

I/O / ICLK

I/O / D0

I/O / D1 / ICE

I/O / OCLK

I/O / OE

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