 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
RT3PE3000L-CG484B Datasheet(PDF) 7 Page - Actel Corporation |
|
||||||||||||||||||||||||||||||
RT3PE3000L-CG484B Datasheet(HTML) 7 Page - Actel Corporation |
|
|
7 / 144 page  Radiation-Tolerant ProASIC3 Device Family Overview Ad vance v0.1 1-3 Advanced Flash Technology The RT ProASIC3 family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with 7 layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. Advanced Architecture The proprietary RT ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The RT ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1): • FPGA VersaTiles • Dedicated FlashROM • Dedicated SRAM/FIFO memory • Extensive CCCs and PLLs • I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the RT ProASIC3 core tile, as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable, allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation- architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of RT ProASIC3 devices via an IEEE 1532 JTAG interface. Figure 1-1 • RT ProASIC3 Device Architecture Overview 4,608-Bit Dual-Port SRAM or FIFO Block VersaTile RAM Block CCC Pro I/Os 4,608-Bit Dual-Port SRAM or FIFO Block RAM Block ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps |
Similar Part No. - RT3PE3000L-CG484B |
|
Similar Description - RT3PE3000L-CG484B |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
