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RTSX-S Datasheet(PDF) 11 Page - Actel Corporation |
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RTSX-S Datasheet(HTML) 11 Page - Actel Corporation |
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11 / 84 page  RTSX-S RadTolerant FPGAs v2.2 1-5 Global Resources Actel’s high-drive routing structure provides three clock networks: hardwired clocks (HCLK), routed clocks (CLKA, CLKB), and quadrant clocks (QCLKA, QCLKB, QCLKC, QCLKD). The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in each R-cell. HCLK cannot be connected to combinational logic. This provides a fast propagation path for the clock signal, enabling the 9.5 ns clock-to-out (pad-to-pad) performance of the RTSX-S devices. The second type of clock, routed clocks, (CLKA, CLKB) are global clocks that can be sourced from either external pins or internal logic signals within the device. CLKA and CLKB may be connected to sequential cells (R-cells) or to combinational logic (C-cells). The last type of clock, quadrant clocks, are only found in the RT54SX72S. Similar to the routed clocks, the four quadrant clocks (QCLKA, QCLKB, QCLKC, QCLKD) can be sourced from external pins or from internal logic signals within the device. Each of these clocks can individually drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. Design Environment The RTSX-S family of FPGAs is fully supported by both Actel's Libero™ Integrated Design Environment (IDE) and Designer FPGA Development software. Actel Libero IDE is a design management environment, seamlessly integrating design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes Synplify® for Actel from Synplicity®, ViewDraw for Actel from Mentor Graphics, ModelSim™ HDL Simulator from Mentor Graphics®, WaveFormer Lite™ from SynaptiCAD™, and Designer software from Actel. Refer to the Libero IDE flow (located on Actel’s website) diagram for more information. Actel's Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes timing-driven place-and-route, and a world-class integrated static timing analyzer and constraints editor. With the Designer software, a user can select and lock package pins while only minimally impacting the results of place-and-route. Additionally, the back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Actel’s integrated verification and logic analysis tool. Another tool included in the Designer software is the ACTgen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. Programming Programming support is provided through Actel's Silicon Sculptor II, a single-site programmer driven via a PC- based GUI. Factory programming is available as well. Low-Cost Prototyping Solution Since the enhanced radiation characteristics of radiation- tolerant devices are not required during the prototyping phase of the design, Actel has developed a prototyping solution for RTSX-S that utilizes commercial SX-A devices. The prototyping solution consists of two parts: • A well-documented design flow that allows the customer to target an RTSX-S design to the equivalent commercial SX-A device • Either footprint-compatible packages or protoyping sockets to adapt commercial SX-A packages to the RTAX-S package footprints This methodology provides the user with a cost-effective solution while maintaining the short time-to-market associated with Actel FPGAs. Please see the application note Prototyping for the RTSX-S Enhanced Aerospace FPGA for more details Table 1-1 • RTSX-S Global Resources RT54SX32S RT54SX72S Routed Clocks (CLKA, CLKB) 2 2 Hardwired Clocks (HCLK) 1 1 Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD) 04 |
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