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A54SX32P-2PL208 Datasheet(PDF) 28 Page - Actel Corporation |
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A54SX32P-2PL208 Datasheet(HTML) 28 Page - Actel Corporation |
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28 / 64 page  SX Family FPGAs 1- 24 v3.2 A54SX08 Timing Characteristics Table 1-17 • A54SX08 Timing Characteristics (Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70°C) Parameter Description '–3' Speed '–2' Speed '–1' Speed 'Std' Speed Min. Max. Min. Max. Min. Max. Min. Max. Units C-Cell Propagation Delays1 tPD Internal Array Module 0.6 0.7 0.8 0.9 ns Predicted Routing Delays2 tDC FO = 1 Routing Delay, Direct Connect 0.1 0.1 0.1 0.1 ns tFC FO = 1 Routing Delay, Fast Connect 0.3 0.4 0.4 0.5 ns tRD1 FO = 1 Routing Delay 0.3 0.4 0.4 0.5 ns tRD2 FO = 2 Routing Delay 0.6 0.7 0.8 0.9 ns tRD3 FO = 3 Routing Delay 0.8 0.9 1.0 1.2 ns tRD4 FO = 4 Routing Delay 1.0 1.2 1.4 1.6 ns tRD8 FO = 8 Routing Delay 1.9 2.2 2.5 2.9 ns tRD12 FO = 12 Routing Delay 2.8 3.2 3.7 4.3 ns R-Cell Timing tRCO Sequential Clock-to-Q 0.8 1.1 1.2 1.4 ns tCLR Asynchronous Clear-to-Q 0.5 0.6 0.7 0.8 ns tPRESET Asynchronous Preset-to-Q 0.7 0.8 0.9 1.0 ns tSUD Flip-Flop Data Input Set-Up 0.5 0.5 0.7 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.4 1.6 1.8 2.1 ns Input Module Propagation Delays tINYH Input Data Pad-to-Y HIGH 1.5 1.7 1.9 2.2 ns tINYL Input Data Pad-to-Y LOW 1.5 1.7 1.9 2.2 ns Input Module Predicted Routing Delays2 tIRD1 FO = 1 Routing Delay 0.3 0.4 0.4 0.5 ns tIRD2 FO = 2 Routing Delay 0.6 0.7 0.8 0.9 ns tIRD3 FO = 3 Routing Delay 0.8 0.9 1.0 1.2 ns tIRD4 FO = 4 Routing Delay 1.0 1.2 1.4 1.6 ns tIRD8 FO = 8 Routing Delay 1.9 2.2 2.5 2.9 ns tIRD12 FO = 12 Routing Delay 2.8 3.2 3.7 4.3 ns Note: 1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. |
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