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AGL060V2-QN144I Datasheet(PDF) 11 Page - Actel Corporation |
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AGL060V2-QN144I Datasheet(HTML) 11 Page - Actel Corporation |
11 / 212 page IGLOO Low-Power Flash FPGAs v1.3 1 - 7 All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: • Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz • Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz • 2 programmable delay types for clock skew minimization • Clock frequency synthesis (for PLL only) Additional CCC specifications: • Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration (for PLL only). • Output duty cycle = 50% ± 1.5% or better (for PLL only) • Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global network used (for PLL only) • Maximum acquisition time is 300 µs (for PLL only) • Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only) • Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz / fOUT_CCC (for PLL only) Global Clocking IGLOO devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards The IGLOO family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V). IGLOO FPGAs support many different I/O standards—single-ended and differential. The I/Os are organized into banks, with two or four banks per device. The configuration of these banks determines the I/O standards supported. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: • Single-Data-Rate applications • Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications IGLOO banks for the AGL250 device and above support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads. |
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