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EX256-TQ100PP Datasheet(PDF) 1 Page - Actel Corporation |
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EX256-TQ100PP Datasheet(HTML) 1 Page - Actel Corporation |
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1 / 49 page  June 2006 i © 2006 Actel Corporation eX Family FPGAs Leading Edge Performance • 240 MHz System Performance • 350 MHz Internal Performance • 3.9 ns Clock-to-Out (Pad-to-Pad) Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops (Using CC Macros) •0.22 µm CMOS Process Technology • Up to 132 User-Programmable I/O Pins Features • High-Performance, Low-Power Antifuse FPGA • LP/Sleep Mode for Additional Power Savings • Advanced Small-Footprint Packages • Hot-Swap Compliant I/Os • Single-Chip Solution •Nonvolatile • Live on Power-Up • No Power-Up/Down Sequence Required for Supply Voltages • Configurable Weak-Resistor Pull-Up or Pull-Down for Tristated Outputs during Power-Up • Individual Output Slew Rate Control • 2.5 V, 3.3 V, and 5.0 V Mixed-Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength • Software Design Support with Actel Designer and Libero™ Integrated Design Environment (IDE) Tools • Up to 100% Resource Utilization with 100% Pin Locking • Deterministic Timing • Unique In-System Diagnostic and Verification Capability with Silicon Explorer II • Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) • Fuselock™ Secure Programming Technology Prevents Reverse Engineering and Design Theft Product Profile FuseLock Device eX64 eX128 eX256 Capacity System Gates Typical Gates 3,000 2,000 6,000 4,000 12,000 8,000 Register Cells Dedicated Flip-Flops Maximum Flip-Flops 64 128 128 256 256 512 Combinatorial Cells 128 256 512 Maximum User I/Os 84 100 132 Global Clocks Hardwired Routed 1 2 1 2 1 2 Speed Grades –F, Std, –P –F, Std, –P –F, Std, –P Temperature Grades* C, I, A C, I, A C, I, A Package (by pin count) TQFP CSP 64, 100 49, 128 64, 100 49, 128 100 128, 180 Note: *Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings. v4.3 |
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