Core3DES

8

v5.0

Decryption

To begin the process of decrypting data, the following

inputs are set:

1. K[1:64] is set to the third of three cipher sub-keys

("ck3" in Figure 9) to encrypt the data.

2. D[1:64] is set to the ciphertext data ("d1" in Figure

9) to be decrypted.

3. ED is set to logic '0'.

4. EN is set to logic '1'.

After 15 clock cycles of the EN input being held

continuously at a logic '1' value, the KSEL[1:0] outputs

will change from '10' to '01', indicating that the second

of three cipher sub-keys (ck2 in Figure 9) will need to be

presented on the K[1:64] inputs, which must be done by

the rising clock edge of the start of clock cycle 17 (one

complete clock cycle of slack is built into the Core3DES

circuitry). After 31 clock cycles of the EN input being held

at a logic '1', the KSEL[1:0] outputs will change from '01'

to '00', indicating that the first of three cipher sub-keys

(ck1 in Figure 9) will need to be presented on the K[1:64]

inputs, which must be done by the rising clock edge of

the start of clock cycle 33. Note that for decryption, the

order in which the three cipher sub-keys are required

differs from the encryption process (described in the

previous section); cipher sub-key three is required first,

cipher sub-key two is next, and cipher sub-key one is last.

After 48 clock cycles of the EN input being held

continuously at a logic '1' value, the QVAL signal will

transition from logic '0' to logic '1' and remain valid for

one clock cycle, indicating that valid plaintext (un-

encrypted data, shown as q1 in Figure 9) is available on

the Q[1:64] outputs. Note that the decrypted plaintext

data is only available during clock cycle 48, thus the user

must register or latch the data on Q[1:64] using the

QVAL signal as a qualifying register enable or latch

enable.

As shown in Figure 9, continuous decryption is possible.

For example, the second 64-bit ciphertext data word (d2

in Figure 9) can be immediately decrypted by presenting

d2 on the D[1:64] inputs by the rising clock edge of clock

cycle 49 and by presenting the cipher sub-keys ck3, ck2,

and ck1 in the sequence described earlier in this section.

Figure 9 • Example Decryption Sequence

CLK

K[1:64]

D[1:64]

ED

EN

cycle

Q[1:64]

QVAL

KSEL[1:0]

d2

ck3

q1

ck3

d1

Don't care

Undefined

01

ck2

ck1

01

10

10

00

00

10

1

2

15 16

18

17

31 32

34

33

...

...

47 48

50

49

...