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CORE429-SN Datasheet(PDF) 5 Page - Actel Corporation |
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CORE429-SN Datasheet(HTML) 5 Page - Actel Corporation |
5 / 22 page ARINC 429 Bus Interface v5.0 5 where NRx is the number of receive channels, NTx is the number of transmit channels, INT is the function to round up to the next integer, and X and Y are defined in Table 6. Each Channel Configured Differently Use EQ 2 to calculate the number of memory blocks required if each channel is configured differently. Number of memory blocks = INT(FIFO_DEPTH[I]/Y + (INT(LABEL_SIZE[I]/X) + INT(FIFO_DEPTH[I]/Y)), EQ 2 where NRx is the number of receive channels, NTx is the number of transmit channels, INT is the function to round up to the next integer, and X and Y are defined in Table 6. Examples for the ProASIC3/E Device Family If the design has 2 receivers, 1 transmitter, 64 labels for each receiver, 32-words-deep FIFO for each receiver and transmitter, then the number of memory blocks = 2 * (INT (64/512) + INT (32/128)) + 1 * INT (32/128) = 2 * (1 + 1) + 1 * (1) = 5. If the design has 2 receivers, 1 transmitter, 32 labels for receiver # 1, 64 labels for receiver # 2, 32 words-deep FIFO for receiver # 1, 64-words-deep FIFO for receiver # 2, and 64-words-deep FIFO for transmitter, then the number of memory blocks = INT (64/128) + (INT (32/512) + INT (32/128)) + (INT (64/512) + INT (64/128)) = 1 + (1 + 1) + (1 + 1) = 5. Core429 Overview Core429 provides a complete and flexible interface to a microprocessor and an ARINC 429 data bus. Connection to an ARINC 429 data bus requires additional line drivers and line receivers. Core429 interfaces to a processor through the internal memory of the receiver. Core429 can be easily interfaced to an 8-, 16- or 32-bit data bus. Look-up tables loaded into memory enable the Core429 receive circuitry to filter and sort incoming data by label and destination bits. Core429 supports multiple (configurable) ARINC 429 receiver channels, and each receives data independently. The receiver data rates (high or low speed) can be programmed independently. Core429 can decode and sort data based on the ARINC 429 Label and SDI bits and stores it in FIFO. Each receiver uses programmable FIFO to buffer received data. Core429 supports multiple (configurable) ARINC 429 transmit channels and each channel can transmit data independently. Default Mode This is the recommended mode and allows the user to configure the core with user-defined transmit and receive channels. Functional Description The core has three main blocks: Transmit, Receive, and CPU interface. The core can be configured to provide up to 16 transmit and receive channels. Table 6 • Memory Parameters Device Family X Y Fusion 512 128 ProASIC3/E 512 128 ProASICPLUS 256 64 Axcelerator/RTAX-S 512 128 I0 = NTx 1 – ∑ I0 = NRx 1 – ∑ |
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