ARINC 429 Bus Interface

2

v5.0

General Description

Core429 provides a complete Transmitter (Tx) and

Receiver (Rx). A typical system implementation using

Core429 is shown in Figure 1.

The core consists of three main blocks: Transmit, Receive,

and

CPU

Interface

(Figure 1).

Core429

requires

connection to an external CPU. The CPU interface

configures the transmit and receive control registers and

initializes the label memory. The core interfaces to the

ARINC 429 bus through an external ARINC 429 line driver

and line receiver. A detailed description of the Rx

interface and Tx interface is provided in the "Functional

Description" section on page 5.

External Components

There are two external components required for proper

operation of Core429:

•

Standard ARINC 429 line driver

•

Standard ARINC 429 line receiver

ARINC 429 Overview

ARINC 429 is a two-wire, point-to-point data bus that is

application-specific

for

commercial

and

transport

aircraft. The connection wires are twisted pairs. Words

are 32 bits in length and most messages consist of a

single data word. The specification defines the electrical

standard and data characteristics and protocols.

ARINC 429 uses a unidirectional data bus standard (Tx

and Rx are on separate ports) known as the Mark 33

Digital Information Transfer System (DITS). Messages are

transmitted at 12.5, 50 (optional), or 100 kbps to other

system elements that are monitoring the bus messages.

The transmitter is always transmitting either 32-bit data

words or the Null state.

The ARINC standard supports High, Low, and Null states

(Figure 2). A minimum of four Null bits should be

transmitted between ARINC words. No more than 20

receivers can be connected to a single bus (wire pair) and

no less than one receiver, though there will normally be

more.

Figure 3 on page 3 shows the bit positions of ARINC

data.

Each ARINC word contains five fields:

•

Parity

Contents

General Description .................................................... 2

ARINC 429 Overview .................................................. 2

Core429 Device Requirements ................................... 3

Memory Requirements ............................................... 4

Core429 Overview ...................................................... 5

Default Mode ............................................................. 5

Functional Description ............................................... 5

Legacy Mode ............................................................... 7

Core Parameters ......................................................... 8

I/O Signal Descriptions ............................................... 8

Default Mode Operation ......................................... 10

Legacy Operation ..................................................... 13

Status Register .......................................................... 15

CPU Interface Timing for Default Mode ................. 16

Clock Requirements .................................................. 17

Core429 Verification ................................................ 17

Testbench .................................................................. 17

Line Drivers ............................................................... 18

Line Receivers ........................................................... 18

Loopback Interface ................................................... 18

Development System ................................................ 18

Ordering Information .............................................. 19

List of Changes ......................................................... 20

Datasheet Categories ............................................... 21

Figure 1 •

Typical Core429 System—One Tx and One Rx

Figure 2 •

ARINC Standard

Actel FPGA

CPU

Glue

Logic

CoreARINC429

Rx I/F

Tx I/F

RxHi

RxLo

TxHi

TxLo

CPU

Interface

12

3

4

5

6

7

8

910

32

1

1

1

1

1

1

0

00

0

0

Bit

Number

"A" Leg

"B" Leg

Data

A

B

High

Null

Low

+5

0

–5

High

Null

Low

+5

0

–5