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CORECORDIC-EV Datasheet(PDF) 6 Page - Actel Corporation |
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CORECORDIC-EV Datasheet(HTML) 6 Page - Actel Corporation |
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6 / 18 page  CoreCORDIC CORDIC RTL Generator 6 v2.0 Depending on the CORDIC mode (rotation or vectoring), the sign-controlling logic watches either the RegY or the RegA sign bit. Based on EQ 8 and EQ 9 on page 2, it decides what type of operation (addition or subtraction) needs to be performed at every iteration. The arctan LUT keeps a pre-computed table of the arctan(2-i) values. The number of entries in the arctan LUT equals the desirable number of iterations, n. The word-serial CORDIC engine takes n + 1 clock cycles to complete a single vector coordinate conversion. Parallel Pipelined Architecture This architecture presents an unrolled version of the sequential CORDIC algorithm above. Instead of reusing the same hardware for all iteration stages, the parallel architecture has a separate hardware processor for every CORDIC iteration. An example of the parallel CORDIC architecture configured for rotation mode is shown in Figure 5. Each of the n processors performs a specific iteration, and a particular processor always performs the same iteration. This leads to a simplification of the hardware. All the shifters perform the fixed shift, which means these can be implemented in the FPGA wiring. Every processor utilizes a particular arctan value that can also be hardwired to the input of every angle accumulator. Yet another simplification is an absence of a state machine. The parallel architecture is obviously faster than the sequential architecture described in the "Word-Serial Architecture" section on page 5. It accepts new input data and puts out the results at every clock cycle. The architecture introduces a latency of n clock cycles. Figure 5 • Parallel CORDIC Architecture xn yn +/– –/+ >> 0 >> 0 d0 Reg Reg d0 x0 y0 +/– Reg d0 a0 arctan (20) d0 >> 1 >> 1 d1 d1 x1 y1 >> 2 >> 2 x2 y2 >> n–1 >> n-1 xn–1 yn–1 d2 d2 dn–1 dn–1 +/– –/+ Reg Reg +/– –/+ Reg Reg +/– –/+ Reg Reg +/– Reg d1 a1 arctan (2–1) d1 +/– Reg d2 a2 arctan (2–2) d2 +/– Reg dn–1 an–1 arctan (2n–1) dn–1 an |
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