CoreSDLC

v4.0

9

Power Control Register (pcon)

GSC Mode Register (gmod)

Table 8 • pcon Register

MSB

LSB

–

–

–

garen

xrclk

gfien

–

–

Table 9 • pcon Register Bit Functions

Bit

Symbol

Function

7:5

–

Not used

4

garen

Auxiliary receive enable

1– The reception of back-to-back frames is enabled. The receiver is not disabled after receiving the EOF

flag when this bit is set.

0 – Prevents reception of back-to-back frames. The receiver is disabled after receiving the EOF flag.

3

xrclk

External receive clock

1 – External clock and NRZ encoding scheme used by receiver

0 – Internal clock generator and NRZI encoding used by receiver

2

gfien

Flag idle enable

1 – Idle flags (01111110) are generated between transmitted frames representing the sequence

01111110 01111110. . .

0 – No idle flag generation

1:0

–

Not used

Note: This register has unimplemented bits (–). Unless otherwise noted, if these bits are read they will return '0'. Writing to these bits has

no effect.

Table 10 • gmod Register

MSB

LSB

xtclk

m1

m0

a1

ct

pl1

pl0

–

Table 11 • gmod Register Bit Functions

Bit

Symbol

Function

7

xtclk

External transmit clock

1 – External clock and NRZ encoding used by transmitter

0 – Internal clock generator and NRZI encoding used by transmitter

6:5

m1

m0

Mode select

00 – normal

01 – raw transmit

10 – raw receive

11 – not allowed

4

a1

Address length

1 – 16-bit addressing is used

0 – 8-bit addressing is used

3

ct

The CRC type

1 – 32-bit CRC is used

0 – 16-bit CRC (CRC-CCITT) is used