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LT3506AEDHD-PBF Datasheet(PDF) 7 Page - Linear Technology |
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LT3506AEDHD-PBF Datasheet(HTML) 7 Page - Linear Technology |
7 / 24 page LT3506/LT3506A 3506afb OPERATIO The LT3506 is a dual, constant frequency, current mode buck regulator with internal 2A power switches. The two regulators share common circuitry including voltage reference and oscillator. In addition, the analog blocks on both regulators share the VIN1 supply voltage, but are otherwise independent. This section describes the opera- tion of the LT3506. If the RUN/SS (run/soft-start) pins are both tied to ground, the LT3506 is shut down and draws 30μA from VIN1. Internal 2μA current sources charge external soft-start capacitors,generatingvoltagerampsatthesepins.Ifeither RUN/SS pin exceeds 0.6V, the internal bias circuits turn on, including the internal regulator, 800mV reference and 575kHz master oscillator. In this state, the LT3506 draws 1.8mA from VIN1, whether one or both RUN/SS pins are high. Neither switching regulator will begin to operate until its RUN/SS pin reaches ~0.8V. The master oscillator generates two clock signals of opposite phase. Thetwoswitchersarecurrentmode,step-downregulators. This means that instead of directly modulating the duty cycle of the power switch, the feedback loop controls the peak current in the switch during each cycle. This cur- rent mode control improves loop dynamics and provides cycle-by-cycle current limit. The Block Diagram in Figure 2 shows only one of the two switching regulators. A pulse from the slave oscillator sets the RS flip-flop and turns on the internal NPN bipolar powerswitch.Currentintheswitchandtheexternalinduc- tor begins to increase. When this current exceeds a level determined by the voltage at VC, current comparator C1 resets the flip-flop, turning off the switch. The current in the inductor flows through the external Schottky diode, and begins to decrease. The cycle begins again at the next pulse from the oscillator. In this way the voltage on the VC pin controls the current through the inductor to the output. The internal error amplifier regulates the output voltage by continually adjusting the VC pin voltage. The threshold for switching on the VC pin is 0.75V, and an active clamp of 1.9V limits the output current. The VC pin is also clamped to the RUN/SS pin voltage. As the internal current source charges the external soft-start capacitor, the current limit increases slowly. Each switcher contains an independent oscillator. This slave oscillator is normally synchronized to the master oscillator. However, during start-up, short-circuit or overload conditions, the FB pin voltage will be near zero and an internal comparator gates the master oscillator clock signal. This allows the slave oscillator to run the regulator at a lower frequency. This frequency foldback behavior helps to limit switch current and power dissipation under fault conditions. The switch driver operates from either the input or from the BOOST pin. An external capacitor and diode are used to generate a voltage at the BOOST pin that is higher than the input supply. This allows the driver to fully saturate the internal bipolar NPN power switch for efficient opera- tion. A power good comparator trips when the FB pin is at 90% of its regulated value. The PG output is an open collector transistor that is off when the output is in regulation, al- lowing an external resistor to pull the PG pin high. Power good is valid when the LT3506 is enabled (either RUN/SS pin is high) and VIN is greater than ~3.4V. (Refer to the Block Diagram) |
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