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U3665M-MDP Datasheet(PDF) 1 Page - TEMIC Semiconductors |
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U3665M-MDP Datasheet(HTML) 1 Page - TEMIC Semiconductors |
1 / 9 page U3665M Preliminary Information TELEFUNKEN Semiconductors Rev. A1, 17-Jul-96 1 (9) Baseband Delay Line 64 ms (Improved Version) Application In TV sets, the integrated baseband delay line circuit is suitable for decoders with color-difference signal outputs Description The integrated delay line circuit U3665M is suitable for all chroma decoders with baseband color-difference outputs. It is suitable for PAL-, SECAM- and NTSC-signals as well. The U3665M contains two separate delay lines for processing (R–Y)-output and (B–Y)-output separately. The delay is performed by inter- nally switched capacitors. On-chip postfiltering avoids the need for external filter components. In the case of the U3665M, the postfilter is tuned to Bessel-characteristic. A summing circuitry combines the information of adjacent TV-lines, thus giving an interpolated sum for the PAL-system, storing preceeding lines for the SECAM- system and providing a comb-filtered output for NTSC-signals. Due to internally generated timing, synchronization is easily done by feeding a line-frequent impulse (usually the SC-impulse) to the sync-input of the IC. Features D One line delay time, addition of delayed and non-delayed output signals D Adjustment-free application, VCO without external components D Handles negative or positive color-difference input signals D Clamping of AC-coupled input signals [ ±(R–Y) and ±(B–Y)] D Line-locked by the sandcastle pulse D No crosstalk between SECAM color carriers (diaphoty) D Comb-filtering functions for NTSC color- difference signals D Correction of phase errors in the PAL system SC detector Line memory Shift register Line memory Clamping Clamping VRef VRef S+H S+H LPF LPF + + Control PLL Clock generator 12 11 9 10 (B–Y) (R–Y) VDD1 GND1 3 MHz fSC 5 14 16 1 3 SC pulse (B–Y) (R–Y) VDD2 GND2 94 8846 " " " " Bias Figure 1. Block diagram |
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