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TELCOM SEMICONDUCTOR, INC.

15-BIT, FAST-INTEGRATING CMOS

ANALOG-TO-DIGITAL CONVERTER

TC850

.

Pin Description (Digital)

Chip Select and Chip Enable (CS and CE)

The CS and CE inputs permit easy interfacing to a

variety of digital bus systems. CE is active LOW while CS is

active HIGH. These inputs are logically ANDed internally

and are used to enable the RD and WR inputs.

Write Enable Input (WR)

The write input is used to initiate a conversion when the

TC850 is in demand mode. CS and CE must be active for the

WR input to be recognized. The status of the data bus is

meaningless during the WR pulse, because no data is

actually written into the TC850.

Read Enable Input (RD)

The read input, combined with CS and CE, enables the

3-state data bus outputs. Also, in continuous mode, the

rising edge of the RD input activates an internal byte counter

to sequentially read the three data bytes.

Low/High Byte Select (L/H)

The L/H input determines whether the low (least signifi-

cant) byte or high (most significant) byte of data is placed on

the 3-state data bus. This input is meaningful only when the

TC850 is in the demand mode. In the continuous mode, data

must be read in three predetermined bytes, so the L/H input

is ignored.

Overrange/Polarity Bit Select (OVR/POL)

The TC850 provides 15 bits of resolution, plus polarity

and overrange bits. Thus, 17 bits of information must be

transferred on an 8-bit data bus. To accomplish this, the

overrange and polarity bits are multiplexed onto data bit DB7

of the most significant byte. When OVR/POL is HIGH, DB7

of the high byte contains the overrange status (HIGH =

analog input overrange, LOW = input within full scale). When

OVR/POL is LOW, DB7 is HIGH for positive analog input

polarity and LOW for negative polarity. The OVR/POL input

is meaningful only when CS, CE, and RD are active, and L/

H is LOW (i.e., the most significant byte is selected). OVR/

POL is ignored when the TC850 is in continuous mode.

Continuous/Demand Mode Input (CONT/DEMAND)

This input controls the TC850 operating mode. When

CONT/DEMAND is HIGH, the TC850 performs conversions

continuously. In continuous mode, data must be read in the

prescribed sequence shown in Table I. Also, all three data

bytes must be read within 443-1/2 internal clock cycles after

the BUSY output goes low. After 443-1/2 clock cycles data

will be lost.

When CONT/DEMAND is LOW, the TC850 begins a

conversion each time CS and CE are active and WR is

pulsed LOW. The conversion is complete and data can be

read after the falling edge of the BUSY output. In demand

mode, data can be read in any sequence, and remains valid

until WR is again pulsed LOW.

Busy Output (BUSY)

The BUSY output is used to convey an end-of-conver-

sion to external logic. BUSY goes HIGH at the beginning of

the deintegrate phase and goes LOW at the end of the

conversion cycle. Data is valid on the falling edge of BUSY.

The output-high period is fixed at 836 clock periods, regard-

less of the analog input value. BUSY is active during

continuous and demand mode operation.

This output can also be used to generate an end-of-

conversion interrupt in

µP-based systems. Noninterrupt-

driven systems can poll BUSY to determine when data is

valid.

ANALOG SECTION APPLICATIONS

Component Selection

Reference Voltage

This value yields a full-scale voltage of 3.2768V and resolu-

tion of 100

maintain 15-bit accuracy for the total conversion process;

i.e.,

±1%.

The reference voltage is not limited to exactly 1.6384V,

however, because the TC850 performs a ratiometric con-

version. Therefore, the conversion result will be:

Digital counts =

• 16384.

between 120k

Ω and 150kΩ are acceptable.

25

µA

The full-scale voltage can range from 3.2V to 3.5V. Full-

scale voltages of less than 3.2V will result in increased noise

in the least significant bits, while a full-scale above 3.5V will

exceed the input common-mode range.

Integration Resistor

The TC850 buffer supplies 25

µA of integrator charging

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