ILX3232

January 2009, Ver. 04

The circuit models in Figures 1 and 2 represent the typical ESD testing circuits used for these

methods. The CS is initially charged with the DC power supply when the first switch (SW1) is on. Now that

the capacitor is charged, the second switch (SW2) is on while SW1 switches off. The voltage stored in the

capacitor is then applied through RS, the current limiting resistor, onto the device under test (DUT). In ESD

tests, the SW2 switch is pulsed so that the device under test receives a duration of voltage.

Fig. 2. ESD Test Circuit for IEC1000-4-2

Fig. 3. ESD Test Waveform for IEC1000-4-2

For the Human Body Model, the current limiting resistor (R

S

) and the source capacitor (C

S

) are 1.5kΩ

an 100pF, respectively. For IEC-1000-4-2, the current limiting resistor (R

S

) and the source capacitor (C

S

) are

330Ω an 150pF, respectively. The higher C

S

value and lower R

S

value in the IEC1000-4-2 model are more

stringent than the Human Body Model. The larger storage capacitor injects a higher voltage to the test point

when SW2 is switched on. The lower current limiting resistor increases the current charge onto the test point.

Device Pin

Tested

IEC1000-4-2

Air Discharge

Level

Driver Outputs

Receiver Inputs

±15kV

±15kV

4

4