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IN74HC112AN Datasheet(PDF) 1 Page - IK Semicon Co., Ltd |
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IN74HC112AN Datasheet(HTML) 1 Page - IK Semicon Co., Ltd |
1 / 6 page TECHNICAL DATA IN74HC112A Dual J-K Flip-Flop with Set and Reset ORDERING INFORMATION IN74HC112AN Plastic IN74HC112AD SOIC TA = -55° to 125° C for all packages High-Performance Silicon-Gate CMOS The IN74HC112A is identical in pinout to the LS/ALS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices FUNCTION TABLE Inputs Outputs Set Reset Clock J K Q Q L H X X X H L H L X X X L H L L X X X L * L * H H L L No Change H H L H L H H H H L H L H H H H Toggle H H L X X No Change H H H X X No Change H H X X No Change * Both output will remain low as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously X = Don’t Care PIN ASSIGNMENT LOGIC DIAGRAM PIN 16=VCC PIN 8 = GND Rev. 00 |
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