TECHNICAL DATA

IW4021B

8-Bit Shift Register

High-Voltage Silicon-Gate CMOS

ORDERING INFORMATION

IW4021BN Plastic

IW4021BDW SOIC

The IW4021B is an Edge-Triggered 8-Bit Shift Register (Parallel-to-

Input (CP), an asynchronous active HIGH Parallel Load Input (PL), eight

Information on the Parallel Data Inputs (P0-P7) is asynchronously

loaded into the register while the Parallel Load Input (PL) is HIGH,

in the register is stored on the HIGH-to-LOW transition of the Parallel

Load Input (PL).

When the Parallel Load Input is LOW, data on the Serial Data Input

is shifted one position to the right on the LOW-to-HIGH transition of the

Clock Input (CP).

• Operating Voltage Range: 3.0 to 18 V

PIN ASSIGNMENT

• Maximum input current of 1 μA at 18 V over full package-temperature

range; 100 nA at 18 V and 25

°C

• Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

LOGIC DIAGRAM

PIN 8 = GND

FUNCTION TABLE

SERIAL OPERATION:

t=n+6

t

CP

PL

t=n+7

t=n+8

n

0

0

0

n+1

1

0

1

0

n+2

0

0

0

1

0

n+3

1

0

1

0

1

X

0

PARALLEL OPERATION:

CP

PL

X

X

1

D

D

D

D

D

D

X = don’t care

D = 1 or 0

Rev. 00