TECHNICAL DATA

IN74HC533A

Octal 3-State Inverting

Transparent Latch

High-Performance Silicon-Gate CMOS

ORDERING INFORMATION

IN74HC533AN Plastic

IN74HC533ADW SOIC

The IN74HC533A is identical in pinout to the LS/ALS533. The

device inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LS/ALSTTL outputs.

These latches appear transparent to data (i.e., the outputs change

asynchronously) when Latch Enable is high. The data appears as the

outputs in inverted form. When Latch Enable goes low, data meeting the

setup and hold time becomes latched.

The Output Enable input does not affect the state of the latches, but

when Output Enable is high, all device outputs are forced to the high-

impedance state. Thus, data may be latched even when the outputs are not

enabled.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

PIN ASSIGNMENT

FUNCTION TABLE

Inputs

Output

Output

Enable

Latch

Enable

D

Q

L

H

H

L

L

H

L

H

L

L

X

no

change

H

X

X

Z

X = don’t care

Z = high impedance

LOGIC DIAGRAM

PIN 10 = GND

Rev. 00