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17 page 
Preliminary Data Sheet #: TM061 Page 17 of 48 Rev: P06 Date: 11/22/04 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Detailed Description continued Interrupts Eight interrupts are provided and appear in the INTR_EVENT (0x12) register. Each interrupt can be individually enabled or disabled via the INTR_ENABLE (0x13) register. Each bit enables or disables the corresponding interrupt from asserting the SPI_INT pin. Interrupt events still appear in the INTR_EVENT (0x12) register independent of their enable state. All interrupts are cleared once INTR_EVENT (0x12) register is read. The interrupts provided are: • Any reference changing from available to not available • Any reference changing from not available to available • Xref changing from activity to no activity • Xref changing from no activity to activity • DPLL Mode status change • Reference switch in automatic reference selection mode • Loss of Signal • Loss of Lock Interrupts and Reference change in Autonomous mode – Interrupts can be used to determine the cause of a reference change in autonomous mode. Let us assume that the module is currently locked to REF1. The module switches to REF2 and SPI_INT pin is asserted. The user reads the INTR_EVENT (0x12) register. If the module is operating in autonomous non-revertive mode, the cause can be determined from bits4, 5, 6 and 7. Bit5 is set to indicate Active reference change. If Bit6 is set then the cause of the reference change is Loss of Active Reference. If Bit7 is set then the cause of the reference change is a Loss of Lock alarm on the active reference. If the module is operating in autonomous revertive mode, the cause can be determined from bits1, 4,5, 6 and 7. Bit5 is set to indicate Active reference change. If Bit6 is set then the cause of the reference change is Loss of Active Reference. If Bit7 is set then the cause of the reference change is a Loss of Lock alarm on the active reference. If Bit1 is set then the cause of the reference change is the availability of a higher priority reference. Note: The DPLL Mode Status Change bit (Bit4) is also set to indicate a change in DPLL_STATUS (0x11) register, during an interrupt caused by a reference change. The data in DPLL_STATUS (0x11) register however is not useful in determining the cause of a reference change. This is because bits0-2 of this register always reflects the status of the current active reference and hence cannot be used to determine the status of the last active reference. Interrupts in Manual Mode – In manual operating mode, when the active reference fails due to a Loss of Signal or Loss of Lock alarm, an interrupt is generated. For example, in case of a Loss of Signal, bits4 and 6 of INTR_EVENT (0x12) register would be set to indicate Loss of Signal and DPLL Mode Status Change. The user may choose to read the DPLL_STATUS (0x11) register, though in manual mode bit6 of INTR_EVENT (0x12) register is a mirror of bit0 of DPLL_STATUS (0x11) register. This holds true for a Loss of Lock alarm, where bit7 of INTR_EVENT (0x12) register is a mirror of bit1 of DPLL_STATUS (0x11) register. OCXO/TCXO Calibration The OCXO/TCXO may be calibrated by writing a frequency offset v.s. nominal frequency into the Calibration register. This calibration is used by the synchronization software to create a frequency corrected from the actual OCXO/TCXO output by the value written to the Calibration register. See Register Descriptions and Operation section. |
