8

LT1641-1/LT1641-2

164112fc

Short-Circuit Protection

The chip features a programmable foldback current limit

with an electronic circuit breaker that protects against

short-circuits or excessive supply currents. The current

and SENSE (Pin 7).

To prevent excessive power dissipation in the pass tran-

sistor and to prevent voltage spikes on the input supply

during short-circuit conditions at the output, the current

folds back as a function of the output voltage, which is

sensed at the FB pin (Figure 7).

When the voltage at the FB pin is 0V, the current limit

circuit drives the GATE pin to force a constant 12mV drop

across the sense resistor. As the output voltage at the FB

pin increases, the voltage across the sense resistor in-

creases until the FB pin reaches 0.5V, at which point the

voltage across the sense resistor is held constant at 47mV.

The maximum current limit is calculated as:

For a 0.025

Ω sense resistor, the current limit is set at

1.88A and folds back to 480mA when the output is shorted

to ground.

The IC also features a variable overcurrent response time.

The time required to regulate Q1’s drain current depends

on: Q1’s input capacitance; gate capacitor C1 and com-

pensation resistor R6; and the internal delay from the

SENSE to the GATE pin. Figure 8 shows the delay from a

voltage step at the SENSE pin until the GATE voltage starts

falling, as a function of overdrive.

TIMER

The TIMER pin (Pin 5) provides a method for program-

ming the maximum time the chip is allowed to operate in

current limit. When the current limit circuitry is not active,

the TIMER pin is pulled to GND by a 3

µA current source.

After the current limit circuit becomes active, an 80

µApull-

up current source is connected to the TIMER pin and the

voltage will rise with a slope equal to 77

as the current limit circuit remains active. Once the desired

maximum current limit time is set, the capacitor value is:

C(nF) = 62 • t(ms).

If the current limit circuit turns off, the TIMER pin will be

discharged to GND by the 3

µA current source.

Whenever the TIMER pin reaches 1.233V, either the inter-

nal fault latch is set (LT1641-1) or the autorestart latch is

set (LT1641-2). The GATE pin is immediately pulled to

GND and the TIMER pin is pulled back to GND by the 3

µA

APPLICATIO S I FOR ATIO

SHORT

PIN

TIMER

SENSE

GATE

87

6

54

2

1

3

D1

CMPZ

5248B

GND

PWRGD

PWRGD

FB

R5

10

Ω

5%

ON

R1

49.9k

1%

24V

GND

1641-1 F05

R2

3.4k

1%

C2

0.68

µF

R6,

1k, 5%

0.025

Ω

C1

10nF

R3

59k

1%

R4

3.57k

1%

R7

24k

5%

+

LT1641-1

Q1

IRF530

Figure 5. Typical Application

Figure 6. Power-Up Waveforms