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HEF4020B Datasheet(PDF) 7 Page - NXP Semiconductors |
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HEF4020B Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 13 page HEF4020B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 4 December 2008 7 of 13 NXP Semiconductors HEF4020B 14-stage binary counter 12. Waveforms Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter VDD Typical formula for PD (µW) where: PD dynamic power dissipation 5V PD = 600 × fi + Σ(fo × CL) × VDD2 fi = input frequency in MHz, fo = output frequency in MHz, CL = output load capacitance in pF, VDD = supply voltage in V, Σ(C L × fo) = sum of the outputs. 10 V PD = 2800 × fi + Σ(fo × CL) × VDD2 15 V PD = 8200 × fi + Σ(fo × CL) × VDD2 Measurement points are given in Table 9. Fig 7. Propagation delays, minimum pulse widths, transition and recovery times and maximum clock frequency MR INPUT VI Q0 or Qn OUTPUT tW tPHL trec 1/fmax VM VM VM 001aae591 tPLH tW tt tt tPHL CP INPUT VI VOH VOL VSS VSS Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 8. Test circuit VDD VI VO 001aag182 DUT CL RT G |
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