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WS57C51C-45DMB Datasheet(PDF) 1 Page - STMicroelectronics |
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WS57C51C-45DMB Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 7 page PRODUCT SELECTION GUIDE PARAMETER 57C51C-35 57C51C-45 57C51C-55 57C51C-70 Address Access Time (Max) 35 ns 45 ns 55 ns 70 ns CS to Output Valid Time (Max) 20 ns 20 ns 25 ns 30 ns WS57C51C 2-47 HIGH SPEED 16K x 8 CMOS PROM/RPROM KEY FEATURES • Very Fast Access Time • Pin Compatible with Am27S51 — 35 ns and N82HS1281 • Low Power Consumption • Immune to Latch-Up • Fast Programming — Up to 200 mA • ESD Protection Exceeds 2000 V GENERAL DESCRIPTION The WS57C51C is a High Performance 128K UV Erasable Electrically Re-Programmable Read Only Memory (RPROM). It is manufactured in an advanced CMOS technology which enables it to operate at Bipolar PROM speeds while consuming only 25% of the power required by its Bipolar counterparts. A further advantage of the WS57C51C over Bipolar PROM devices is the fact that it utilizes a proven EPROM technology. This enables the entire memory array to be tested for switching characteristics and functionality after assembly. Unlike devices which cannot be erased, every WS5751C in a windowed package is 100% tested with worst case test patterns both before and after assembly. The WS57C51C provides a low power alternative to those designs which are committed to a Bipolar PROM footprint. It is a direct drop-in replacement for a Bipolar PROM of the same architecture (16K x 8). No software, hardware or layout changes need be performed. VCC A10 A11 A12 A13 CS1/VPP CS2 CS3 CS4 O7 O6 O5 O4 O3 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A12 A13 CS1/VPP CS2 CS3 CS4 NC O7 O6 A5 A4 A3 A2 A1 A0 NC O0 O1 O2 NC O3 NC O4 O5 1 43 2 32 31 30 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TOP VIEW Chip Carrier CERDIP PIN CONFIGURATION ROW DECODER EPROM ARRAY 131,072 BITS COLUMN DECODER SENSE AMPLIFIERS 8 CS3 CS4 OUTPUTS CS1/ VPP A0 - A5 COLUMN ADDRESSES A6 - A13 ROW ADDRESSES 8 6 CS2 BLOCK DIAGRAM Return to Main Menu |
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